<---------------------- EXPANDABLE CROSS ASSEMBLER LINKER --------------> Control File: NINTENDO GAMEBOY 'Z80' (Zilog, Mostek, SGS-ATES). Written By: Michael J Plant, (C) Maxim Technology 1988. Revision: 1.21 (Additional addressing option of (IX) as well as (IX+d)) : REVISED 16/JULY/90 R.TREDOUX FOR NES GAMEBOY MNEMONICS Reference(s): Programming The Z80 (ISBN 0-89588-069-5) by Rodnay Zaks. Zilog Components Data Book. Acknowledge.: Z80 is a registered trademark of Zilog Inc. : NES and GAMEBOY are registered trademarks of NINTENDO Inc. Hardcopy: Document Mode, 63 Lines/Page, No Footer Lines, To Page 11. Basic Spec.: Type: 8 bit Code: 1-4 bytes. Exec Time: 1uS to 4uS typical (@ 4MHZ) CLK: 4MHZ, 6MHZ Power: +5V --------------------------------------------------------------------------- <-------------------------- INSTALL INSTRUCTIONS --------------------------> ;INSTALL Commands 0 MODEL EXP16,PCBYTES 0 FLAG SZHPVNC ;Flag display index (up to 8) 0 FLAGST *10?U ;Optional Flag parameter char's ;------------------------------------------------------------------------- ;TYPE definitions q E<>16SX ALIGN 1 ;2 byte address n EAND 0FFFFFF00H ;1 byte value (range 0..255) ALIGN 0 e E<>16 LOW16 PCMOD NEXT PCREL ;PC relative offset E< -128 E> 127 AND 000FFH ALIGN 0 ^o E> 0FFFFH E< 0FF00H AND 0FFH ALWAYS 2 ;HARDWARE 0FF00H-0FFFFH ADDRESS, LOW BYTE d E<>16S LOW16 E< -128 ;IX/IY Relative offset (1 byte) E> 127 AND 000FFH ALIGN 0 f E<>16S LOW16 E< -128 ;IX/IY Relative offset (1 byte) - inserted before last opcode E> 127 AND 000FFH ALIGN 1 b EAND 0FFFFFFF8H ;BIT select (bit 3-5) LOW16 SHL 3 ALIGN 0 ^x EAND 0FFFFFFC7H ;Allowed value is 00H, 08H.... ALWAYS 1 ;------------------------------------------------------------------------ ;SET definitions r SET 1 ;Register set (1 char) - shifted 3 places - ALWAYS 1st opcode A 111000B B 000000B C 001000B D 010000B E 011000B H 100000B L 101000B ALWAYS 1 s SET 1 ;Register set (1 char) - shifted 3 places - ALWAYS 2nd opcode A 111000B B 000000B C 001000B D 010000B E 011000B H 100000B L 101000B ALWAYS 2 g SET 1 ;Register set (1 char) - A 111B B 000B C 001B D 010B E 011B H 100B L 101B ALWAYS 2 w SET 2 ;Register set (2 char) always affect 2nd opcode BC 000000B DE 010000B HL 100000B SP 110000B ALWAYS 2 v SET 2 ;Register set (2 char) always affect 1st opcode BC 000000B DE 010000B HL 100000B SP 110000B ALWAYS 1 p SET 2 ;PUSH/POP Register set (2 char) AF 110000B BC 000000B DE 010000B HL 100000B ALIGN 0 i SET 2 ;IX/IY select IX 11011101B IY 11111101B ALWAYS 1 x SET 3 ;ReSTart positions code 00H 11000111B 08H 11001111B 10H 11010111B 18H 11011111B 20H 11100111B 28H 11101111B 30H 11110111B 38H 11111111B ALIGN 0 ;------------------------------------------------------------------------ ;MNEMONIC definitions ADC A,(HL) :7,08EH,'Add With Carry,.0' A,g :4,10001gggB A,n :7,0CEH,nnnnnnnnB ADD A,(HL) :7,086H,'Add Excl. carry,??.?0' A,g :4,10000gggB A,n :7,0C6H,nnnnnnnnB HL,w :11,00ww1001B SP,n :4,0E8H,nnnnnnnnB,'SP=SP+e ,**00' AND (HL) :7,0A6H,'Boolean AND Acc ,1.00' g :4,10100gggB n :7,0E6H,nnnnnnnnB BIT b,(HL) :12,0CBH,01bbb110B,'Test Bit State ,U*1U.0.' b,g :8,0CBH,01bbbgggB,:8 CALL q :17,0CDH,qqqqqqqqB,qqqqqqqqB,'Subroutine Call ,.......' Z,q :10/17,11001100B,qqqqqqqqB,qqqqqqqqB NZ,q :10/17,11000100B,qqqqqqqqB,qqqqqqqqB C,q :10/17,11011100B,qqqqqqqqB,qqqqqqqqB NC,q :10/17,11010100B,qqqqqqqqB,qqqqqqqqB CCF . :4,03FH,'Complement Carry,..U..0' CP (HL) :7,0BEH,'Compare Acc ,.1' g :4,10111gggB n :7,0FEH,nnnnnnnnB CPL . :4,02FH,'Complement Acc ,..1..1.' DAA . :4,027H,'BCD Adjust Acc ,..' DEC (HL) :11,035H,'Decrement ,???.?*.' r :4,00rrr101B w :6,00ww1011B DI . :4,0F3H,'Disable Mask-Int,.......' DJNZ e :8/13,010H,eeeeeeeeB,'Dec B & Jump-Rel,.......' EI . :4,0FBH,'Enable Mask-Int ,.......' HALT . :4*n,076H,'Halt CPU Exec. ,.......' STOP . :1,010H,00H INC (HL) :11,034H,'Increment ,???.??.' r :4,00rrr100B w :6,00ww0011B JP (HL) :4,0E9H,'Jump Absolute ,.......' q :10,11000011B,qqqqqqqqB,qqqqqqqqB Z,q :10,11001010B,qqqqqqqqB,qqqqqqqqB NZ,q :10,11000010B,qqqqqqqqB,qqqqqqqqB C,q :10,11011010B,qqqqqqqqB,qqqqqqqqB NC,q :10,11010010B,qqqqqqqqB,qqqqqqqqB JR e :12,018H,eeeeeeeeB,'Jump Relative ,.......' Z,e :7/12,028H,eeeeeeeeB NZ,e :7/12,020H,eeeeeeeeB C,e :7/12,038H,eeeeeeeeB NC,e :7/12,030H,eeeeeeeeB LD (^o.l),A :3,0E0H,nnnnnnnnB,'(FF00H+n)<-A ,........' !q :13,0EAH,qqqqqqqqB,qqqqqqqqB,'Load Reg/Mem ,???.??.' (q),SP :20,08H,qqqqqqqqB,qqqqqqqqB (BC),A :7,002H (DE),A :7,012H (HL),g :7,01110gggB (HL),n :10,036H,nnnnnnnnB A,(^o.l) :3,0F0H,ooooooooB,'A<-(FF00H+n) ,........' !q :13,0FAH,qqqqqqqqB,qqqqqqqqB A,(BC) :7,00AH A,(DE) :7,01AH r,(HL) :7,01rrr110B r,g :4,01rrrgggB r,n :7,00rrr110B,nnnnnnnnB v,q :10,00vv0001B,qqqqqqqqB,qqqqqqqqB SP,HL :6,0F9H A,(C) :2,0F2H,'A<-(FF00H+C) ,........' (C),A :2,0E2H,'(FF00H+C)<-A ,........' A,(HLI) :2,02AH,'Load A from (HL) inc HL ,........' A,(HLD) :2,03AH,'Load A from (HL) dec HL ,........' (HLI),A :2,022H,'Store A in (HL) inc HL ,........' (HLD),A :2,032H,'Store A in (HL) dec HL ,........' LDHL SP,e :3,0F8H,eeeeeeeeB,'HL<-SP+n ,**00' NOP . :4,000H,' ,.......' OR (HL) :7,0B6H,'Boolean OR Acc ,0.00' g :4,10110gggB n :7,0F6H,nnnnnnnnB POP p :10,11pp0001B,'Pop Reg STACK ,.......' PUSH p :11,11pp0101B,'Push Reg STACK ,.......' RES b,(HL) :15,0CBH,086H,'Reset Bit ,.......' b,g :8,0CBH,10bbbgggB RET . :10,0C9H,'Return From CALL,.......' Z :5/11,0C8H NZ :5/11,0C0H C :5/11,0D8H NC :5/11,0D0H RETI . :14,11011001B,'Return Interrupt,.......' RL (HL) :15,0CBH,016H,'Rot Lft Thrgh C ,0.0*' g :8,0CBH,00010gggB RLA . :4,017H,'Rot Lft Thr-C A ,..0..0*' RLC (HL) :15,0CBH,006H,'Rot Lft Brnch C ,0.0*' g :8,0CBH,00000gggB RLCA . :4,007H,'Rot Lft Brn-C A ,..0..0*' RLD . :18,0EDH,06FH,'Rot Left BCD,0.0.' RR (HL) :15,0CBH,01EH,'Rot Rgh Thrgh C ,0.0*' g :8,0CBH,00011gggB RRA . :4,01FH,'Rot Rgh Thr-C A ,..0..0*' RRC (HL) :15,0CBH,00EH,'Rot Rgh Brnch C ,0.0*' g :8,0CBH,00001gggB RRCA . :4,00FH,'Rot Rgh Brn-C A ,..0..0*' RRD . :18,0EDH,067H,'Rot Right BCD,0.0.' RST x :11,xxxxxxxxB,'Restart Call ,.......' ^x :11,11xxx111B SBC A,(HL) :7,09EH,'Sub With Carry ,?.1' A,g :4,10011gggB A,n :7,0DEH,nnnnnnnnB SCF . :4,037H,'Set Carry Flag ,..0..01' SET b,(HL) :15,0CBH,11bbb110B,'Set Bit ,.......' b,g :8,0CBH,11bbbgggB SLA (HL) :15,0CBH,026H,'Shift Left Arith,0.0*' g :8,0CBH,00100gggB SRA (HL) :15,0CBH,02EH,'Shift Rght Arith,0.0*' g :8,0CBH,00101gggB SRL (HL) :15,0CBH,03EH,'Shift Rght Logic,0.0*' g :8,0CBH,00111gggB SUB (HL) :7,096H,'Subtract Excl. C ,.1' g :4,10010gggB n :7,0D6H,nnnnnnnnB SWAP (HL) :4,0CBH,00110110B,'SWAP NIBBLES OVER,........' g :2,0CBH,00110gggB XOR (HL) :7,0AEH,'Boolean XOR Acc ,0.00' g :4,10101gggB n :7,0EEH,nnnnnnnnB ;------------------------------------------------------------------------