Who are the Computer Architects?

last updated: 21 December 1999

1. Considerations about the list
2. Supercomputer processors
3. VLIW processors
4. Independence architecture processors (Intel IA-64)
5. Mainframe processors
6. Minisupercomputer processors
7. Minicomputer and Superminicomputer processors (16 and 32-bit)
8. Workstation processors (32 and 64-bit)
9. Wintel processors (16 and 32-bit)
10. Multimedia processors
11. Java processors
12. Stack processors
13. Embedded processors
14. DSP processors
15. Selected game processors
16. Acknowledgements
17. Revision history

Considerations about the list

I am publishing this list to identify recent processor architects and recognize their work.

As one architect told me, people outside the design circles (sometimes even meaning company executives) have bought into a myth: "in the '60's, Computer Architecture Giants Walked The Earth, and we pathetic lame-o descendants aren't fit to carry their slide rules." I agree that it is a myth. It shouldn't be the case that just Gene Amdahl, Gerrit Blaauw, Fred Brooks, John Cocke, Seymour Cray, and Mike Flynn are recognized as the giants in computer architecture and everyone else today is a midget. There are many tremendously gifted people at work in instruction set design and especially processor microarchitecture (cf. section 1.2 of Hennessy and Patterson, CA:AQA 2e).

The current format is a listing of an instruction set architecture (ISA) and its architect(s), followed by implementations of that ISA and the associated microarchitect(s)/designer(s). The processors I am listing have been available for sale commercially, and in most instances, I have categorized the processors by company. Although I may extend the list back into and before the 1970's, the current list mainly includes late 1980's and 1990's ISAs and microprocessor implementations. I especially want to highlight high-performance (superscalar and VLIW) implementations.

However, I approach this task recognizing several limitations of the list:

• The list may leave someone out and/or perhaps lead to disagreement over the amount of someone's contribution. I apologize in advance for mistakes and omissions.
• There are many excellent academic and industrial researchers in computer architecture who have greatly influenced the design of current processors but who have not served as the lead designer of a specific ISA or chip. I leave their recognition to another list.
• I probably should do more to highlight a distinction made to me by John Mashey. For some designs, there is a "clear architect who is THE driving force" (perhaps even two people). In other designs, there might be a team of people involved, and the architect has more of a role of "collecting things together and being the editor of the architecture document". In the later case, the success of an architecture can really be credited to the wise assembly of a lot of different people's expertise. I hope that listings of architecture teams will convey some of this distinction.
• I will leave innovative processor designs that did not make it to completion and market to footnotes or to another list (e.g., see Dead Supercomputer Society).
• There are many interesting computer systems that are based on existing processors (e.g., Cray T3E using Alpha processors, SGI Origin using MIPS R10000 processors). I am not listing the system designers, but they are truly computer architects, too.
• I am just starting the market segments other than workstations and Wintel. There are a plethora of processors in these other markets, and I will see how successful I can be in putting together a concise but accurate list.

I would appreciate help in the form of your corrections, additions, and other suggestions. I am especially interested in published articles of these kinds:

• The history of a design, especially as it names the design team members and their roles. Articles that contain interviews with the architects that go beyond "marketing talk" would be excellent.
• What was learned from the successes and especially the "mistakes" in a given design. (Yale Patt attempted to gather this kind of material in the January 1989 special issue of IEEE Computer: "Real Machines: Design Choices/Engineering Tradeoffs".)

Finally, I know of three excellent (although dated) books that describe the environment and decision-making constraints (i.e., politics) facing an architect:

• Charles Bashe, Lyle Johnson, John Palmer, and Emerson Pugh. IBM's Early Computers. Cambridge, MA: MIT Press, 1986.
• Emerson Pugh, Lyle Johnson, and John Palmer. IBM's 360 and Early 370 Systems. Cambridge, MA: MIT Press, 1991.
• Tracy Kidder. The Soul of a New Machine. Boston: Little, Brown, & Co., 1981. [story of the Data General MV/8000]

Mark Smotherman

Supercomputer processors

... much more to do!

Astronautics

• Astronautics ZS-1 (Decoupled Architecture), 1987 - Jim Smith

Control Data Corporation (CDC)

• 6600, 1964 - Seymour Cray (see Gordon Bell's talk on Cray)
• 7600, 1969 -
• Star-100 - Thornton
• ...
• Cyber 170 -
• Cyber 180/990 - Ron Hintz (chief architect)
  • Tom Lane, Jim Smith, ...
  • used branch prediction and "conditional issue" (i.e., speculative execution) [first use of two-bit counter for branch history?]

Cray

• Cray-1, 1976 - Seymour Cray (see Gordon Bell's talk on Cray)
• X-MP, 1985 [Lester Davis and/or Steve Chen? as system architect]
  • See M. August, G. Brost, C. Hsiung, and A. Schiffleger, "Cray X-MP: The Birth of a Supercomputer," IEEE Computer, January 1989, pp. 45-54.
• Y-MP, 1988

Fujitsu

Hitachi

NEC

Tera

• Tera (multithreaded VLIW) - Burton Smith
  • descended from Deneclor HEP and SRC Horizon

Texas Instruments

• TI-ASC, 1972 -
  • See H. Cragon and W.J. Watson, "The TI Advanced Scientific Computer," IEEE Computer, January 1989, pp. 55-64.

VLIW processors

... more to do!

See see multimedia processor section.

Apollo (see workstation processor section)

Culler Scientific Systems

• Culler-7, 1986 - Glen Culler (lead), Bob Pearson, John Richardson, Mike McCammon, and Dave Probert (see Culler-7 web page)

Cydrome

• Cydrome Cydra 5, 1988 - Bob Rau, Ross Towle, David Yen, and Wei Yen
  • Ross Towle - compiler
  • worked for Gary Beck on the processor: Joe Bratt, John Brennan, Steve Wilson, and Gulbin Ezer
  • worked on the memory system - Ed Wolff and Norman Yeung
  • worked for Jack Kister on the I/O system: Gil Lauer, Jack Mills, David Roe, and Mohammed Seth
  • others who contributed to hardware and software efforts: Jim Dehnert, Stimson Ho, and Mike McNammara
  • Peter Hsu and Mike Schlansker did the groundwork for the Cydra 10 (which did not get further than a paper design before the company folded)
  • Peter Hsu went to MIPS and the MIPS R8000 was greatly influenced by the Cydra designs
• See Bob Rau, David Yen, Wei Yen, and Ross Towle, "The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-offs," IEEE Computer, January 1989, pp. 12-35.

FPS (Floating Point Systems)

• AP-120B, 1975 (array processor for signal processing) - Alan Charlesworth and George O'Leary
• FPS-164, 1980 (array processor for scientific computing)

Intel

• Intel i860 (N10), 1989 - Les Kohn
  • RISC-like processor with dual instruction mode (LIW)
  • See discussion of design team in Tekla Perry, "Intel's secret is out," IEEE Spectrum, April 1989, pp. 22-28. A picture of the design team is on the cover of this issue.
  • exposed pipelines were criticized for their effect on context switch complexity and latency, later the chip was used by many as a graphics accelerator
• i860XP (N11) - David Perlmutter (Chief), Michael Kagan (lead)
  • an extension to N10, with MP support (enable physical snooping), new process, and better performance.

Multiflow

• Multiflow TRACE, 1988 - Dave Papworth (co-chief), Paul Rodman (co-chief), and John O'Donnell
  • Based on ideas of Josh Fisher
  • compiler folks: John Ruttenberg, Geoff Lowney, Tom Karzes, Stefan Freudenberger, Cindy Collins, Woody Lichtenstein (worked on the Culler-7)
  • hardware team: Sandra Joshi, Richard Lethin, John Feehrer, Mauro Lupero, Bob Colwell
  • operating systems team: Bob Nix, Doug Gilmore, Ben Cutler, Chris Ryland

Tera (see supercomputer processor section)

Texas Instruments

• "VelociTI" VLIW architecture - Ray Simar (lead)
  • TMS320C6xx - Ray Simar (lead)

Independence architecture processors

Name due to Josh Fisher and Bob Rau. Explicitly encoded information on instruction independence is placed in the instruction format by the compiler. Difference from VLIW is that hardware does the scheduling. Example prototype is Burton Smith's Horizon processor. ... more to do!

Intel

• Intel IA-64, 1997 - John Crawford, Don Alpert, and Hans Mulder (Intel), Jerry Huck, Bill Worley, and Rajiv Gupta (HP)
  • NOTE: relatively little has been revealed about the details or history of the efforts that actually led to the IA-64; I hope to include more information as it becomes available over the next year or two.
  • cooperation announced in June 1995
  • based on PA-Wide-Word effort at HP Labs guided by Bill Worley, 1990-1993; also called SP-PA (Super-Parallel Processor Architecture) [see Joel Birnbaum's talk at Microprocessor Forum]
  • introduced EPIC (Explicitly Parallel Instruction Computing) philosophy at 1997 Microprocessor Forum
  • See separate page on historical background

  • Merced, 1998 - first implementation

Texas Instruments

• "VelociTI" VLIW architecture - Ray Simar (lead) (see VLIW processor section)

Mainframe processors

to be done

Burroughs

• B5000, 1963 - Bob Barton
• B5500, 1964 -
• B6500, 1969 -
• B7500 -
• B5700, 1970 -
• B6700 -
• B7700 -
• A-series -

• B1700 - Bob Barton and W.T. Wilner
  • B1712, B1726 - First generation hardware implementing a reloadable microarchitecture. Interpreters were kept in main memory and were swapped by the OS (MCP) as different language codes ran.
  • B1835, B1855, B1865 - upgrades with a cache memory for the interpreter
  • B1910, B1955, B1965 - TTL-based implementations of the architecture. The B1900 was designed by a group led by Ed (Bud) Keeley. Bill Sprouse and Frank Williams were the main hardware designers with Steven Tsai, Steven Amic, and Steve Wilson also working on the CPU. The I/O subsystem group was led by Jerry Wygant. Todd Barth did the disk controller.

Control Data Corporation (CDC)

• 1604, 1960 - Seymour Cray (see Gordon Bell's talk on Cray)
• 3600 - Seymour Cray

Digital Equipment Corporation (DEC)

• PDP-10 - see DEC entry in minicomputer section

General Electric (GE) / Honeywell Information Systems (HIS)

• Several GE papers in Winter 1995 IEEE Annals of the History of Computing
• Honeywell acquired GE computer business in 1970

• ERMA (check-processing system for Bank of America, based on MICR) prototype at SRI, 1955 - Tom Morrin (SRI); production model was GE-100, 1959 - Barney Oldfield; later upgraded to GE-210
• GE-302/312 (industrial control), 1957 - Arnold Spielberg
• GE-225 (derived from 312), 1962 - Arnold Spielberg; later 215 and 235 (DTSS, 1964) models added; model 265 was a 235 with DATANET 30 terminal controller

• GE-635, 1963 - John Couleur
  • genesis was in military work on MISTRAM computer, ca. 1959
  • See John Couleur, "The core of the Black Canyon Computer Corporation," IEEE Annals of the History of Computing, 17, 4, 1995, pp. 56-60.
  • ran GECOS; other models included 615 and 625
  • renamed Honeywell 6000 series (GECOS renamed GCOS); some models extended with decimal/COBOL-oriented inst. set called EIS
  • follow-ons were Series 60/Level 66, then DPS-66
• GE-645 (MULTICS), 1965 - John Couleur (GE) and Edward Glaser (MIT)
  • Frank Fahrlander wrote a system simulation; Jim Haynes headed up the 645 hardware prototype; G.A. Oliver worked on the design of the segmentation scheme; and, Ed Thelen helped design the GIOC
  • John Couleur invented the TLB and indicates that this was an important factor in MIT and Bell Labs choosing GE over IBM for Project MAC
  • added advanced segmented and paged memory system along with protection rings to 635 processor; initial plans for 32 protection rings reduced to 8 rings in final hardware; 645 ran fairly slow (wags said MULTICS = "Multiple Useless Large Tables in Core Simultaneously"); users beyond Project MAC allowed on single operational system at MIT in 1969
  • follow-ons were Honeywell 6180 in 1972, then Series 60/Level 68, then DPS-68, then DPS-8/M
  • Multics Repository at Stratus Computer
  • Tom Van Vleck's MULTICS pages

International Business Machines (IBM)

• 650, 1953 - Ernest Hughes (chief architect) and Frank Hamilton (chief designer)
• 701, 1953 - Nat Rochester (chief architect) and Jerrier Haddad (engineering manager); see the April 1983 special issue of the Annals of the History of Computing
• 702/705, 1953/1954 - Werner Buchholz
• 704, 1954 - Gene Amdahl
• NORC, 1954 (Naval Ordnance Research Calculator) - Byron Havens (chief engineer)
• 1401, 1959 - many people involved with major contributions from Francis Underwood
• 1620 -
• 7070 -
• 7080 -
• 709/7090 -
• 7040/7044 -
• 7094 -
• System/360, 1964 ("360 degrees of data processing") - - Gene Amdahl, Fred Brooks, and Gerrit Blaauw
  • model 20 -
  • model 30 -
  • model 40 -
  • model 50 - John Hipp (engr. mgr.), Pete Fagg (systems mgr.)
  • model 65 - Joe Brown (engr. mgr.), Pete Fagg (systems mgr.)
  • model 75 - Phil Stoughton (engr. mgr.), Pete Fagg (systems mgr.)
  • model 67 - Joe Brown (engr. mgr.), Gene Amdahl (address relocation)
  • model 9x - Mike Flynn, Robert Tomasulo (FP unit)
    • highly parallel FP unit; first [?] use of fetching down taken and untaken branch paths
  • model 85 - Stan Pitkowsky (CPU mgr.); Don Gibson, Carl Conti, and Jim Shelly worked on cache
• S/370 - ..., Richard Case, ...
• 4300 -
• 3033 -
• 3081 -
• 3090 - Julian Thomas, Werner Bucholz, and Ron Smith (architects), Les Garcia (engineering), Stuart Tucker (I-element and vector unit)
• ES/9000
  • model 520 - Liptay
• S/390 G4

Univac

• ERA 1101/1102, 1950 -
• 1103/1103A, 1953/1956 - Arnold Cohen (with involvement by Seymour Cray)
• 1105, 1958 -
• 1107, 1962 -
• 1108, 1966 -
• 1110, 1970 -
• bought by Sperry

Minisupercomputer processors

... more to do!

Alliant

• FX/8, 1985
  • The ISA was basically an emulated Motorola 68012, augmented with vector instructions and parallel processing constructs. The special parallel processing features (hardware, self-scheduled, DO ALL and DO ACROSS functions) were inspired by work done at University of Illinois and further developed by Alliant's founders, especially Ron Gruner and Craig Mundie.
  • The primary architect for the vector ISA augmentations was Mat Myszewski, with contributions from Josh Rosen and Stan Lackey, who were the chief hardware implementers for the CPUs (CEs in Alliant-speak).
  • Mike Ziegler was the primary architect for the overall system configuration and the cache and memory system in particular.
  • The parallel processing hardware (Concurrency Control Unit) and the instruction set extensions that made use of it were architected by Mat Myszewski and Mike Ziegler. Jim Veres was the primary implementer of this hardware and also contributed to the design.
  • Jim Veres was also responsible for the overall IO system architecture.
  • Stan Lackey, Jim Veres, and Mike Ziegler, "Supercomputer Expands Parallel Processing Options," Computer Design, August 15, 1985, p. 76.

Ardent

• Titan, 1988 - Bell, Miranker, Rubinstein, and Sanguinetti?
  • G. Miranker, J. Rubinstein, and J. Sanguinetti, "Squeezing a Cray-class supercomputer into a single-user package," COMPCON, San Francisco, Feb. 1988, pp. 452-456.
  • G. Bell, G. Miranker, and J. Rubinstein, "Supercomputing for one," IEEE Spectrum, 25, 4, April 1988, pp. 46-50.
  • R. Allen, "Unifying vectorization, parallelization, and optimization: The Ardent compiler," Proc. 3rd ICS, Boston, May 1988, pp. 176-184.
  • J. Sanguinetti, "Micro-analysis of the Titan's operation pipe," Proc. ICS, St. Malo, July 1988, pp. 190-196.
  • T. Diede, C. Hagenmaier, G. Miranker, and J. Rubinstein, "The Titan graphics supercomputer architecture," IEEE Computer, 21, 9, Sept. 1988, pp. 13-31.
  • G. Miranker, J. Rubinstein, and J. Sanguinetti, "Getting it right the first time: The Ardent design methodology," COMPCON, San Francisco, Feb. 1989, pp. 529-533.
  • B. Borden, "Graphics processing on a graphics supercomputer," IEEE Computer Graphics and Applications, July 1989, pp. 56-62.
  • R. Allen, "Exploiting multiple granularities of parallelism in a computer," COMPCON, San Francisco, Feb. 1990, pp. 634-640.
  • Dan Siewiorek and Phil Koopman, The Architecture of Supercomputers: Titan, a case study, Academic Press, 1991.
  • merged with Stellar to form Stardent

Stardent

• merger of Stellar and Ardent
• became Kubota Pacific ...

Supertek

• S-1 - (there was a COMPCON paper) - Mike Fang
• acquired by Cray and the S-1 was relabelled as Cray XMS; the Supertek S-2 design became the Cray YMP-EL

Stellar

• GS-1000, 1986 (4-way multithreading with dual-issue from each stream) - Bill Poduska, Michael Sporer, Todd Basche, Peter Oppen, and Brian Apgar
  • M. Sporer, F. Moss, and C. Mathias, "An introduction to the architecture of the Stellar graphics supercomputer," COMPCON 1988, pp. 464-467.
  • merged with Ardent to form Stardent

Minicomputer and Superminicomputer processors

... more to do!

Data General

• DG Nova, 1969 - Henry Burkhardt III
  • The Nova was the first 16-bit small computer to use a multi-register architecture, with 4 registers, 2 of which could be used as index registers. It had a symmetric instruction set, a clean IO structure and occupied 5 1/4" in a 19" rack configuration. In 1969, its list price was about $7,000 with an 8Kb memory.
• DG Nova 2 - Dave Bernstein and Mike Druke
• DG Nova 3 - Dave Bernstein
• DG Nova 4 - Dave Grondalski
• DG Supernova - Larry Seligman and Ron Gruner (first minicomputer to use solid state memory)
• DG microNova - Gardner Hendrie
• DG microNova 200 - Dave Bernstein (a bit-slice implementation of the Nova instruction set crammed into the microNova PCB form factor)
• DG Nova 1200 - Ron Gruner
• DG Nova 800 - Larry Seligman
• DG Eclipse - Ron Gruner, Steve Wallach, etc.
• DG microEclipse - Dave Bernstein (an implementation using a two-level control store to work around the package pinout limitations of the day)
• DG FHP - Rich Belgard, Gerry Clancy, Dick Bratt, Larry Katz, Tom Jones, others (not marketed, the North Carolina-based project described in Tracy Kidder's book)
• Data General MV 8000 - Steve Wallach (described in Tracy Kidder's book)
• Data General MV 10000 -

Digital Equipment Corporation (DEC)

• See C. Gordon Bell, J. Craig Mudge, and John E. McNamara, Computer Engineering: A DEC View of Hardware Systems Design, Digital Press, 1978, for a wonderful history of DEC systems
• 18-bit computer family
  • PDP-1, 1960 - Ben Gurley (head), Harlan Anderson, Dick Best, Ken Olsen, Stan Olsen, and Bob Savell; influenced by MIT TX-0
  • PDP-4, 1962 - Gordon Bell; influenced by MIT LINC
  • PDP-7, 1964
  • PDP-9, 1968
  • PDP-15, 1970
• PDP-2 name reserved for a 24-bit computer which was never built
• 36-bit computer family
  • PDP-3, 1960 - paper design, one built by a customer
  • PDP-6, 1964
  • PDP-10 (KA10), 1967
  • KI10 (1060), 1972
  • KL10 (1080), 1975
  • 2040/2050, 1977?
  • 2020, 1978?
• 12-bit computer family
  • PDP-5, 1963 - Gordon Bell and Alan Kotok; Edson DeCastro did the logic design; influenced by the MIT LINC
  • PDP-8, 1965
  • PDP-12 - switched between PDP-8 and LINC instruction sets
  • PDP-14
• 16-bit computer family, PDP-11 - Gordon Bell
  • PDP-11/20, 1970
  • PDP-11/05, 1972
  • PDP-11/45, 1972
  • PDP-11/70, 1975
  • LSI-11, 1975
  • F-11, 1979
  • J-11, 1983
• 32-bit computer family, VAX - William Strecker
  • VAXA group met in 1975, composed of Gordon Bell, Peter Conklin, Dave Cutler, Bill Demmer, Tom Hastings, Ricky Lary, Dave Rodgers, Steve Rothman, and Bill Strecker as chief architect
  • TTL-based implementations
    • VAX-11/780, 1978 (5 MHz)
    • VAX-11/750, 1980
    • VAX-11/730, 1982
  • ECL-based implementations
    • 8600, 1984 (12.5 MHz) - first VAX design with overlapped operand decoding and fetching; see DTJ August 1985
    • 8200, 1986
    • 8800/8700/8500, 1986
      • pipelined the microinstructions
      • I-box and E-box - Jim Keller, project leader
      • FPU - John Zurawski and Anil Jain
      • see DTJ February 1987
    • 9000, 1989 (code named Aquarius, 62.5 MHz) - "mainframe" VAX with vector processing
      • design started in 1983; RISC-like load/store architecture within the E-box; the I-box acted as a preprocessor and translated VAX instructions into simpler internal instructions for the E-box as well as decoded and fetched operands
      • original team members - David Fite, Tryggve Fossum, Bill Grundmann, Rick Hetherington, Dwight Manley, John Murray, Bill Smith, and David Webb
      • I-box - John Murray, project leader; David Fite, branch prediction, inst. fetch, inst. decode; Mark Firstenberg and Mike McKeon
      • E-box - Ron Salett, project leader; Bill Grundmann, Larry Herman, Ginny Lamere, Elaine Fite, Dan Sterling, Eileen Samberg, Mark Haq, and Matt Adiletta
      • M-box - Dave Webb, Maurice Steinman, Joe Macri, Brad Hollister, and Basheer Ahmed
      • V-box - Dileep Bhandarkar, chief architect for vector processing; Francis McKeen, project leader; Richard Brunner, Bimal Patil, William Rodgers, and Greg Yoder
      • service processor - Michael Evans, project leader; Karen Benard, Stephen Conway, David D'Antonio, Susan DesMarais, Matthew Goldman, Paul Leveille, and Brian Rost
      • TLB and cache design - Rick Hetherington, project leader
      • performance modeling - Dwight Manley
      • see DTJ Fall 1990
    • other mid-range ECL projects, ultimately cancelled due to the progress in CMOS clock rate, were BVAX, Argonaut, and Raven
  • CMOS-based implementations
    • microVAX, 1985 - see DTJ March 1986
    • CVAX, 1987 - used in VAX 6200/6300; see DTJ August 1988
    • Rigel, 1989 - used in VAX 6400/4300; see DTJ Spring 1990
    • Mariah, 1990 - used in VAX 6500
    • NVAX, 1991 (83.3 MHz) and NVAX+, 1991 (90.9 MHz)
      • based on microarchitecture of VAX 9000
      • NVAX used in VAX 6600 and various 4x00 models; NVAX+ used in VAX 7600/10600
      • Michael Uhler (chief architect), Debra Bernstein, Larry Biro, John Brown, John Edmondson, Jeffrey Pickholtz, and Rebecca Stamm
      • see DTJ Summer 1992
  • VAX development ended in 1996
• PRISM, Alpha - see DEC entry in workstation section
• Mica (high performance video chip) - John Kowaleski

Prime

• Bill Poduska, founder; architecture derived from Honeywell 16-bit computers with influence also from Multics (e.g., protection rings); first architects were Walter Jones, who went on to IPL to design a 3090 ECL based machine, Paul Jones, who went to Stellar, and Mike Sporer. Bill Poduska went on to start up Apollo.
• Prime 950 series - Paul Rodman and Dave Papworth

Rational

• R1000 - Mike Devlin and Dave Stevenson
  • Rational was founded by Paul Levy and Mike Devlin in 1981; Dave Bernstein joined to lead the development team a year later. It may have been the only commercially successful high-level-language-specific architecture.

Tandem

• Tandem T16 - Michael Green, Joel Bartlett, Jim Katzman, etc.

Workstation processors

Includes 32-bit and 64-bit processors. Some of these were called supermicrocomputers in the 1980's.

Apple/IBM/Motorola PowerPC

• PowerPC - Rich Oehler (IBM, with Cathy May and Ed Silha), Keith Diefendorff (with Motorola at the time), Ron Hochsprung (Apple), and John Sell (with Apple at the time)
  • started in 1991
  • Marty Hopkins also played a large part in PPC
  • Richard Oehler and Michael Blasgen, Evolution of PowerPC architecture video, UVC, October 1992
• implementations
  • 601, 1993 - Charles Moore and John Muhich
    • Keith Diefendorff, PPC 601 video (Hot Chips V), UVC, August 1993
  • 603, 1994 - Brad Burgess, Russ Reininger, and Jim Kahle
  • 603e, 1995 - Brad Burgess and Robert Golla
  • 604, 1994 - Peter Song
    • Marvin Denman, PPC 604 video (Hot Chips VI), UVC, August 1994
  • 604e, 1996 - Marvin Denman (chief) and Mike Snyder (memory system/bus architect)
  • 620, 1995? - Don Waldecker, Chin Ching Kau, Dave Levitan, maybe Paul Rossbach
  • 740/750 (G3, Arthur), 1997 - Brad Burgess
  • Mach5 - Marvin Denman (chief) and Mike Snyder (memory system/bus architect)

AMD 29K (Advanced Micro Devices)

• AMD 29000 - Brian Case and Ole Moller (initial contributors); also Gigy Baror, Philip Freidin, Smeeta Gupta, Mike Johnson, Cheng-Gang Kong, Tim Olson, and David Sorensen; managerial support from Paul Chu and Bill Harmon
  • 29000, 1987 - David Witt
    • 3 bus, integer only, no d-cache, i-cache was a branch target cache
    • 29005 - cost-reduced 3-bus 29000, missing the BTC and MMU
  • 29027 (FPU), 1987 - Tim Flaherty and Bob Perlman
  • 29050, 1990 - Bob Perlman (lead), Mike Johnson, and Tim Olson
    • included 29000 and 29027, but was more than just an integration
  • unreleased superscalar 29K processor - Mike Johnson
    • was described at 1994 Microprocessor Forum and then used as the core of the AMD K5
  • 29030/29035/29040 (see embedded processor section)

Apollo

• Bill Poduska and Dave Nelson architected the packet-plexor domain network which became Apollo.
• DN3000
• PRISM (3-wide LIW), 1988 - Barry Flahive, Rick Bahr, and John Yates
  • John Yates contributed the multi-issue idea. PRISM was a 3-wide machine -- in each successive clock tick, you could do a floating-point add, a floating-point multiply, and an integer operation (typically a LOAD, for instance of two floating point registers). Perfectly balanced for single-precision Linpack or FFT.
  • DN10000 - the first (and last) model, 54 MIPS, 36 megaflops in 1989.
    • Paul Mageau and Andy Milia were chiefly responsible for the memory system. Doug Voorhies, Olin Lathrop, and Dave Kirk were chiefly responsible for the graphics system.

DEC

• PRISM, 1989 - Wayne Cardoza, +?
• Alpha - Dick Sites and Rich Witek
  • task force for extending VAX and VMS in 1988; Alpha design started in 1989
  • Richard Sites, Alpha AXP Architecture, Digital Technical Journal, Vol 4 No 4, 1992
  • a case history of developing the architecture was written up by R. Comerford, "How DEC developed Alpha," IEEE Spectrum, July 1992, pp. 26-31.
  • Dick Sites and Dirk Meyer, Alpha architecture video, UVC, April 1992
• implementations
  • 21064 (EV-4), 1992 - Rich Witek (lead)
    • Jim Montanaro, Design of the Alpha 21064 CPU Chip video, UVC, April 1992
    • Mark Rosenbluth, Alpha 21066 video (Hot Chips V), UVC, August 1993
  • 21164, 1995 - John Edmondson (lead during design), Pete Bannon, and Jim Keller (lead during advanced development)
    • Beth Cooper, lead cache designer; Gilbert Wolrich, FPU; Ronald Preston, instruction unit; Paul Gronowski, integer execution unit
    • IEEE Micro article
    • John Edmondson, 21164 Microarchitecture video (Hot Chips VI), UVC, August 1994
    • Gregg Bouchard and Pete Bannon, Design Objective of the 0.35-micron Alpha 21164 Microprocessor (Hot Chips 8 slides)
  • 21164PC, 1997 - Pete Bannon (lead)
  • 21264, 1998 - Jim Keller (lead)

(The cover art for the February 1993 special issue of CACM on "Digital's Alpha Chip Project" has a 1967 FIA endurance racing Gulf Mirage M1 [a lightweight version of the Ford GT40, built by John Wyer's team] pictured for the DEC Alpha; however, it is incongruously drag racing. Was this some kind of inside joke?
... Two years later, Dick Sites writes in the Digital Tech. Journal [special 10th anniv. issue, 1995, pp. 5-6] that he'd like to see Alpha thought of as an express-delivery truck -- fast but "commonplace" -- rather than as a race car -- which is "blazingly fast, but not seen in your own neighborhood".)

HP

• HP PA-RISC 1.0 - Bill Worley (lab manager) and Michael Mahon (head of architecture team)
  • first called "Spectrum" and started by Joel Birnbaum
  • original team members: Allen Baum, Hans Jeans, Russell Kao, Ruby Lee, Michael Mahon, Terrence Miller, Steve Muchnick, and Bill Worley
  • Terrence Miller - compiler mgr.; Steve Boettner - OS mgr.; Mike Gardner - hardware design mgr.; Fred Luiz - I/O mgr.; Tony Lukes - perf. analysis mgr.; Dan Magenheimer - simulator; Russell Kao - prototype; Craig Hansen - FP architcture
  • Michael Mahon, HP PA-RISC video, UVC, June 1987
  • Michael Mahon, PA-RISC Design Issues video, UVC, April 1992
  • see the feature article at HPL on "Bill Worley: A Computer Architecture Wizard"
• implementations
  • HP 3000/840
  • ...

• PA-RISC 1.1 - Michael Mahon and Jerry Huck
• MAX-2 multi-media instructions - Ruby Lee
  • IEEE Micro article
  • Ruby Lee, Multimedia acceleration video, UVC, March 1995
• implementations
  • PA 7000, 1989 - team
  • PA 7100 (superscalar), 1992 - team
  • PA 7100LC (superscalar, on-chip 1K icache), 1994 - team
    • Stephen Undy, 7100LC video (Hot Chips V), UVC, August 1993
    • HP Journal April 1995 issue (with PA 7100LC articles)
  • PA 7200 (superscalar, 2K on-chip dcache), 1994 - team
    • HP Journal February 1996 issue (with PA 7200 articles)
  • PA 7300LC (superscalar, dual 64K on-chip caches), 1996 - team
    • HP Journal June 1997 issue (with PA 7300LC articles)

• PA-RISC 2.0 - Michael Mahon and Jerry Huck
• implementations
  • PA 8000 (superscalar), 1996 - team
    • IEEE Micro article
    • Ashok Kumar, The HP PA-8000 RISC CPU: A High Performance Out-of-Order Processor (Hot Chips 8 slides)
    • HP Journal August 1997 issue (with PA 8000/8200 articles)
  • PA 8200 (superscalar), 1997 - team
  • PA 8500 (superscalar, 1M + 512K on-chip caches), 1998? - team
  • future processor roadmap

"In the architecture stage, all of our work has always been done with teams, including hardware, software, and technology experts, often sitting side-by-side. At the heart of our principles is the synergy between the compiler and the hardware, with the compiler relied upon to help avoid hardware bottlenecks and critical paths, and the architectural hardware mechanisms developed to reduce stalls, delays, and critical paths in the code." -- from Joel Birnbaum's talk at 1997 Microprocessor Forum

Intergraph

• Intergraph Clipper
  • C100, 1985 - Howard Sachs, Walt Hollingsworth, and James Cho
  • C300, 1987 -
  • C400 (superscalar), 1991 -
  • work abandoned in 1993, after Andy Grove assured Intergraph chairman Jim Meadlock of availability of Intel chips, see AP news story about current lawsuit

IBM

• 801
  • Joel Birnbaum started a project in early 1975 within the Research Division of IBM to do a machine based on John Cocke's ideas for a simple machine: load-store architecture, execute (delayed) branches, and split cache; the project took on the 801 name because the T.J. Watson Research Center building number is 801
  • John Cocke and Marty Hopkins worked on the early definition which had two- and four-byte ops and 16 GPRs
  • George Radin became manager afer Joel Birnbaum was named director of the Computer Science Dept.
  • Hardware team: Frank Carrubba (manager), Paul Stuckert, Norman Kreitzer, Richard Freitas, and Kenneth Case
  • Compiler team: Marty Hopkins (manager), Richard Goldberg, Peter Oden, Philip Owens, Peter Markstein, and Greg Chaitin
  • OS team: Richard Oehler (manager) and Albert Chang
  • Bill Worley contributed significantly through the years
  • Marty Hopkins:

    Ideas came from many sources and a lot of things were tried that didn't pan out. Examples were doing all protection in software and data base memory. We also started our own programming language, pl.8, which had an optimizing compiler. We invented the idea of doing register allocation by graph coloring. Greg Chaitin was the leader but I sometimes think that half the lab contributed ideas. The one problem Greg couldn't solve in a clean fashion was spilling when there were too few registers. I decided to see what a 32 register machine would look like. This led to all four byte ops which in turn made for a more regular machine and thus a faster cycle time. This is only one example of how software and hardware considerations were treated equally to get something better.

    "The [final] instruction formats were the same that I first drew up to accommodate 32 registers. The general flavor of decision making was collegial and informal. We also had a great crew who worked with us outside of Research. Phil Hester of IBM in Austin adopted the old 16 register machine which became Romp (RT/PC). Later on Austin did the RS/6000 with us. This was based on a Research variant called America. I can't begin to list all the people who contributed. Further ripples went out to PowerPC with Apple and Motorola as well as the AS/400 version of RS/6000. There were many variations that never saw the light of day."

  • M. Hopkins, "A Perspective on the 801/Reduced Instruction Set Computer," IBM Systems Journal, vol. 26, no. 1, 1987, pp. 107-121.
  • G. Radin, "The 801 minicomputer," Proc. ASPLOS-I, Palo Alto, March 1982, pp. 39-47.
• IBM Power - (John Cocke?) Rich Oehler +? (Andrew Heller)
  • arose from ideas of
    • John Cocke ( IBM Stretch [ca. 1960], IBM ACS [ca. 1967], and IBM 801 [ca. 1975])
    • Tilak Agerwala (Cheetah/Panther)
    • Greg Grohoski (America, 1985)
  • original America team: Greg Grohoski (lead), Marc Auslander, Al Chang, Marty Hopkins, Peter Markstein, Vicky Markstein, Mark Mergen, Bob Montoye, and Dan Prener
  • quote from IBM interview with John Cocke:

    Trimble: I know that many people from IBM Research went to Austin to make the RS/6000 happen. Who were some of the players from Research?

    Cocke: Well, of course Andy Heller worked very hard on that project. He had been a very vocal proponent of RISC from day one. Al Chang contributed many, many ideas in both hardware and operating system software. In the compiler area, Peter Markstein was a source of many novel ideas, and Greg Chaitin wrote the compiler register allocator. Then there were Greg Grohoski, who did the timer work, and Fred Blount who did a lot of the overall planning.

  • Phil Hester, RS/6000 video, UVC, Aug. 1990
  • [first use of register renaming?]
• implementations
  • RIOS, 1989 - Greg Grohoski
    • America with IEEE floating point
    • icache and branch processing - Charles Moore (lead), Ed Broufarah, and C.C. Lee
    • integer (fixed-point) unit - Jim Kahle (lead), Larry Thatcher, Dennis Gregoire, Paul Harvey, and Brian Bakoglu
    • floating-point unit - Myhong Nguyenphu (lead), Daniel Cocanougher, Richard Fry, Pat Mills, Oscar Mitchell, and Troy Hicks
  • RSC, 1992 - Charles Moore?
  • Power2 - Greg Grohoski, Warren Maule, Larry Thatcher, and a few others
    • David Shippy, Power 2+ video (Hot Chips VI), UVC, August 1994
  • P2SC, 1997 -
  • Power3, 1998 - (execute both taken and not-taken paths speculatively?)
• IBM P2/PPC extensions for AS/400-PPC - Andy Wottreng and Mike Corrigan
  • AS/400-PPC -
    • PPC AS A10 (50MHz, 77MHz), A30 (154 MHz), A35 (100MHz 125MHz)
    • RISC 40s 2109 ??
  • what is RS64? (A35?)

(see also Apple/IBM/Motorola PowerPC above)

Intel

• Intel iAPX 432 - Justin Rattner (chief), Roger Swanson, and George Cox
  • others involved include Kevin Kahn, Fred Pollack, Dan Hammerstrom, and Konrad Lai
  • implementation - (Steve Domenik ?)
  • an ambitious but ultimately unsuccessful design that has been used to (unnecessarily, IMHO) discredit capability-based processor design
  • see the excellent post mortems:
    • Bob Colwell, Ed Gehringer, and Doug Jensen, "Performance Effects of Architectural Complexity in the Intel 432," ACM Trans. on Computer Systems, vol. 6, no. 3, August 1988, pp. 296-339.
    • Ed Gehringer and Bob Colwell, "Fast Object-Oriented Procedure Calls: Lessons From the Intel 432," ISCA-13, Tokyo, 1986, pp. 92-101.
  • also - selected April 1995 comp.arch traffic discussing the 432
  • (would be interesting to compare "capability-induced slowdown" between native IBM Power2 vs. IBM AS/400-PPC)
  • see Eric Smith's list of papers on the 432
• i860 (see VLIW processor section)
• i960 (see embedded processor section)
• 386,486,Pentium, Pentium Pro, etc. (because of market presence, see Wintel processor section)
• Merced (see independence arch. processor section)

MIPS

• MIPS-I, 1986 - Craig Hansen, chief architect
  • much influenced by Stanford MIPS - John Hennessy
  • team members:
    • John Hennessy, Larry Weber, and Fred Chow (compilers and related ISA issues)
    • John Mashey, Mike Demoney, and Steve Stone (OS-related issues, e.g., MMU, interrupts)
    • Steve Przyblski (cache issues)
    • Chris Rowen, John Moussouris, and Skip Stritter
• MIPS-II, 1990 - Craig Hansen, chief architect
  • with many suggestions made by Earl Killian, George Taylor, and others
• MIPS-III (64-bit arch.), 1991 - Earl Killian, chief architect
  • John Hennessy was the impetus for MIPS III and suggested some of the ways in which it could be done.
• MIPS-IV - Peter Hsu
  • started at SGI before the SGI/MIPS merger, although they consulted with MIPS.
• MIPS-V (many FP opts.), 1995 - Earl Killian finalized it as the chief architect; contributions by Bill Huffman and Peter Hsu
• MDMX, 1996 - the Digital Media ASE (Application Specific Extension)
  • The impetus for this came from Tim Van Hook and Henry Moreton within SGI. Peter Hsu participated. Several people, including Iain McClatchie and Catharine Van Ingen helped create the first architecture documents for it.
• MIPS-V (FP paired-singles), 1996 -

• implementations
  • R2000, 1986 - Craig Hansen, John Moussouris, Tom Riordan, and Chris Rowen
  • R2010 (FPU), 1986 - Craig Hansen, Ed Hudson, Mark Johnson, and others
  • R3000, 1988 - Craig Hansen, Tom Riordan and Ed Hudson
  • R3010 (FPU), 1988 - essentially identical to R2010
  • R6000, 1989 - George Taylor; other people involved were Mike Farmwald and Allen Roberts

  • R4000/4400, 1991/1992 - Peter Davies, Earl Killian, and Tom Riordan
    • "superpipelined" impl. of MIPS-IV - 8-stage pipeline

  • R8000 (TFP), 1994 - Peter Hsu (lead)
    • an SGI project that was folded into the MIPS product line (e.g., compare the different fused-multiply-add definitions on the R8000 and the R10000)
    • There is a direct connection of the basic ideas of the Cydrome Cydra 5 and the R8000. Very different implementations but the basic ideas were the same.
    • Cydra folks: Peter Hsu, Ross Towle, John Brennan, Jim Dehnert (and Joe Bratt joined later); Multiflow folks: Paul Rodman and John Ruttenberg
    • Peter Hsu, SGI TFP video (Hot Chips V), UVC, August 1993

  • R10000, 1996 - Chris Rowen and Ken Yeager
    • aggressive superscalar
    • IEEE Micro article)
  • R12000, 1998? -

  • R4200/4300, 1993 -
    • Barbara Zivkov, R4200 video (Hot Chips V), UVC, August 1993
    • adapted for Nintendo 64 (see selected game processor section)
  • R4600/4700, 1994 - Earl Killian and Tom Riordan
  • R5000, 1996 - Earl Killian and Tom Riordan
  • QED RM7000, 1997 - Tom Riordan

Motorola 68K/88K

• 68000, 1980 - Skip Stritter (lead architect), John Zolnowsky, and Tom Gunter (design manager)
  • Skip Stritter and David Leitch began the instruction set definition, and John Zolnowsky did most of the detailed work. The instruction set design was based heavily on Len Shustek's PhD thesis. Len, Skip, and John had worked together on their PhDs at Stanford (all under Forest Baskett?).
  • logic design and microcode - Nick Tredennick
  • bus controller - Tom Gunter
  • bus protocol and TTL breadboard - Les Crudele
  • circuit design - Doyle McAlister and Richard Crisp
  • circuit simulation - Mike Spak
  • software performance evaluation - Paul Lee
  • see E. Stritter and T. Gunter, "A Microprocessor Architecture for a Changing World: The Motorola 68000," IEEE Computer, Feb. 1979, pp. 43-52.
  • Nick Tredennick has written about the design effort in "Experiences in Commercial VLSI Microprocessor Design," Microprocessors and Microsystems, October 1988, pp. 419-432.
• 68881/2 (FPU) - Joel Boney, Van Shahan, Ashok Someshwar (sp?), and Clay Huntsman
• 68010, 1983 - John Zolnowsky (inst. set extensions) and Doug MacGregor (microcode)
• 68020, 1985 - Bill Moyer, Dave Mothersole, John Zolnowsky, and Doug MacGregor (microcode)
• 68030 - Joel Boney (architecture design manager), Doug MacGregor, Bill Moyer, and Sharon Lamb (who got things started)
  • microcode by Raju Vegesna, microcode assembler by Ed Rupp
• 68040, 1989 - Van Shahan was the main architect
• 68060, 1993 - Joe Circello
  • Joe Circello, 68060 video (Hot Chips VI), UVC, August 1994

• 88100 - Mitch Alsup, Yoav Talgam, Jim Klingshirn, Carl Dobbs, Janet Sooch
  • 88200 CMMU - Mitch Alsup, Eli Haddad, Claude Mogahani (sp?), Jim ????
• 88110 (2-way superscalar), 1991 - Keith Diefendorff (chief), Willie Anderson (graphics and FP extensions), and Bill Moyer (memory system)

National Semiconductor

• National Semiconductor 32K - Dan O'Dowd and Les Kohn
  • 32016/16032 - Avraham Menachem (microarchitecture and chip design), Asher Kaminker (microcode), and Yoav Lavy (BIU, processor buses, external MMU, and interrupt controller)
  • 32332 - Ran Talmudi
  • 32532, 1987 - Uri Weiser, Don Alpert, Gigi Licht, Jonathan Levy (BIU, MMU, and dcache), and Sidi Yom Tov (design manager)
    • See B. Maytal, S. Iacobovici, D. Alpert, D. Biran, J. Levy, and S.Y. Tov, "Design Considerations for a General Purpose Microprocessor," IEEE Computer, January 1989, pp. 66-76.
    • See D. Alpert, J. Levy, and B. Maytal, "Architecture of the NS32532 Microprocessor," Proceedings ICCD, October 1987, pp. 168-172.
  • 32732 (a.k.a. 32764 and Swordfish, superscalar design, not delivered as N32K family member), 1991 - Don Alpert (see Swordfish web page and CompactRISC)
• (see embedded processor section)

SPARC

• SPARC versions 7/8, 1986/1990 - Robert Garner, chief architect
  • much influenced by the UC Berkeley RISC I and RISC II work of Dave Patterson, Manolis Katevenis, and Bob Sherburne
  • started in 1984 when Bill Joy (VP of Sun R&D) brought in Dave Patterson (Berkeley RISC) as a consultant
  • v7 architecture team members: Robert Garner (chief architect), Anant Agrawal and Joan Pendleton (hardware), Steve Kleiman (operating systems), Steve Muchnick (languages), David Hough (floating point), and Bill Joy ("jack of all trades and chief tie-breaker")
  • advisors: Faye Briggs, Will Brown, John Gilmore, Dave Goldberg, Don Jackson, Tom Lyon, Masood Namjoo, Dave Patterson, Wayne Rosing, K.G. Tan, Richard Tuck, Dave Weaver, and Alex Wu
  • Steve Muchnick - compiler manager and in charge of overall performance; Steve Kleiman - Unix port technical lead; Dock Williams - Unix port; Will Brown - simulator
• see the summer 1988 special issue of SunTechnology (vol. 1, no. 3) for "The SPARC Papers". The "/work.group" column (pp. 33-37) describes the development of the architecture. On p. 33 there is a picture of the design team around Eric Schmidt's red Ferrari. (The SPARC papers were also published as a book by Springer-Verlag, Ben Catanzaro, editor, 1991.)
• Dave Patterson and Wayne Rosing, SPARC video, UVC, June 1989
• in early design meetings Muchnick ruled out a graph coloring register allocator for the initial compilers, and, following Patterson's advice, a decision was made that register windows should be included in the architecture as a way to ensure that operands stayed in registers; however, by the time the first systems shipped, the Sun compilers were to a point where better register allocation was a feasible option [see D. Patterson and C. Sequin, "Retrospective: RISC I: A Reduced Instruction Set Computer," in G. Sohi (ed.), 25 Years of the International Symposia on Computer Architecture: Selected Papers, ACM Press, 1998]
• implementations
  • 16.67 MHz Fujitsu gate-array, 1986
    • IU (MB86900) - Anant Agarwal and Masood Namjoo
    • FP control (MB86910, controlled two Weitek data path chips) - Don Jackson
    • processor board for Sun 4/200 - Robert Garner and Ed Kelly
  • 33 MHz Cypress 7C600, 1990
    • IU (CY7C601) -
    • FP control (CY7C608, controlled TI FPU chip) -
  • ...
  • Metaflow Lightning/Thunder (see Metaflow web page)
  • MicroSPARC, 1991 -
  • TI SuperSPARC (Viking), 1992 - Greg Blanck
  • TI SuperSPARC 2, 1995 -
  • Ross HyperSPARC, 1993 - Raju Vegesna (spec) and Jim Monaco (simulator)
    • Generation 1: Pinnacle -> Colorado 3 -- Peter Jewett, Greg Gregorio, Sarangan Padalkar, Haytham Samarchi, Mike Seningen, Sang Yoo
      • Pinnacle - 55, 60, 66 MHz versions in Cypress 0.65 micron
      • Colorado 1 - 90, 100 MHz versions in Fujitsu 0.50 micron
      • Colorado 2 - 125 MHz version in Fujitsu 0.45 micron
      • Colorado 3 - 150, 166 MHz versions in Fujitsu 0.40 micron
    • Generation 2: Colorado 4 - Colorado 5 (new sequencer and on-chip data cache) -- Mitch Alsup, Greg Gregorio, Sarangan Padalkar, Haytham Samarchi
      • Colorado 4 - 180, 200 MHz versions in Fujitsu 0.35 micron
      • Colorado 5 - 250+ MHz versions in NEC 0.25 micron
  • Sun MicroSPARC
  • Fujitsu TurboSPARC, 1996

• SPARC version 9
  • a large committee with over 100 meetings
  • major contributors - Dave Ditzel (chairman), Joel Boney (vice chairman, and chairman at the end), Dave Weaver, Winfried Wilcke, Robert Yung, Bill Joy, Steve Chessin, Steve Krueger, and Steve Kleiman
  • Dave Ditzel, SPARC Version 9 video, UVC, Sept. 1992
• implementations
  • Sun UltraSPARC I, 1995 - Les Kohn, Marc Tremblay, Guillermo Maturana, and Robert Yung
    • IEEE Micro article
  • UltraSPARC II, 1996 - Les Kohn, Marc Tremblay
  • UltraSPARC IIi - Kevin Normoyle
  • UltraSPARC III - Gary Lauterbach
  • UltraSPARC IV -
  • UltraSPARC V - Dan Leibholz...
  • HaL SPARC64, 1995 - Hisashige Ando (design manager), Winfried Wilcke, and Mike Shebanow

• VIS, 1992 - Les Kohn, G. Maturana, Marc Tremblay, A. Prabhu, and G. Zyner, with early contributions by Tim van Hook, Robert Yung, and Bill Joy
  • IEEE Micro article

Weitek

• XL processor - Craig Hansen
• 1064/65/66/67 (FP data paths) - Craig Hansen
  • used for both the original SPARC and MIPS R2000 implementations

Zilog

• Z80 - Masatoshi Shima
• Z8000 - Bernard Peuto (architect)
  • Masatoshi Shima (logic designer); Hiroshi Yonezawa (MMU); Ross Freeman (peripherals); also contributions by Judy Estrin
  • See B. Peuto, "Architecture of a New Microprocessor," IEEE Computer, Feb. 1979, pp. 10-21.
  • See M. Shima, "Demystifying Microprocessor Design," IEEE Spectrum, July 1979, pp. 22-30.
• Z80,000 - John Banning and Don Alpert
  • See D. Alpert, "Powerful 32-Bit Micro Includes Memory Management," Computer Design, October 1983, pp. 213-220.

Multimedia processors

... more to do!

Chromatic Research

• MPact 1, 1995 - Steve Purcell
  • IEEE Micro article
  • Paul Kalapathy, Hardware/Software Interaction on the Mpact Media Processor (Hot Chips 8 slides)
  • Mediaware firmware was a year late, but recently specialized firmware was developed for DVD in three months and will be used by Gateway
• MPact 2, 1997 -
  • doubles the clock speed from 62 to 125 MHz, adds a 32-bit floating-point unit, 35-stage 3-D pipeline, and 2 KB of texture cache
  • Toshiba will use MPact 2 core in embedded DRAM with low power

MicroUnity

• MicroUnity MediaProcessor - Craig Hansen
  • IEEE Micro article

Philips

• TriMedia - Gert Slavenburg
  • evolved from LIFE processor
  • Gerrit A. Slavenburg, Selliah Rathnam, and Henk Dijkstra, The Trimedia TM-1 PCI VLIW Mediaprocessor (Hot Chips 8 slides)

Wintel processors

Because of large market, these are Intel x86 (IA-32) compatible processors. more...

AMD (Advanced Micro Devices)

• AMD K5 - Mike Johnson
  • IEEE Micro article
• AMD/NexGen K6 - Greg Favor
  • AMD started internal K6 work as an extension of the K5 base, but this was discarded in favor of buying NexGen and using their Nx686 design relabelled as K6
• AMD K6 -
  • see The Anatomy of a High-Performance Microprocessor (K6-2 3D-Now! case study)
• AMD Athlon (K7) - Dirk Meyer...
• AMD K8 - Jim Keller....

Cyrix

• Cyrix 486 chips - Mark Bluhm and Ty Garibay
• 5x86 (M1sc) -
• 5gx86 (MediaGX) - Forrest Norrod
• 6x86 (M1) - Mark Bluhm and Ty Garibay
  • in-order superscalar design
• 6x86MX / MII (M2) - Dan Green
  • M1 core with a new memory subsystem and BTB, and added the MMX instructions
  • Robert Maher, Multimedia Instruction Set Extensions for a 6th Generation Processor (Hot Chips 8 slides)
  • MII had a few minor changes from original M2
• MXi (graphics integrated with Cayenne core) - Doug Beard
• MIII (M3) - Ty Garibay and Mike Shebanow started the design and then Greg Grohoski took over the project
  • out-of-order design

IDT

• IDT-C6, 1997 - Terry Parks and Glenn Henry
• C6+ -

Intel

• Intel 8086 and 8088 - Stephen Morse and Bruce Ravenel
  • S.P. Morse, B.W. Ravenel, S. Mazor, and W.B. Pohlman, "Intel Microprocessors -- 8008 to 8086," IEEE Computer, October 1980, pp. 42-60.

    from the acknowledgements section: Many people played significant roles in the development of these processors. Hence, it is not possible to single out a few for all the credit. However, if forced to choose those people who played the most significant roles on each chip, we can name the following: M.E. (Ted) Hoff was the architect and Federico Faggin the chip designer of the 4004. Stanley Mazor contributed to the 4004 architecture as well as to the architectures of the 8008 and 8080. Hoff and Hal Feeney were the major contributors to the 8008 development. Faggin managed the development of the 8080 and participated in defining its architecture, with Masatoshi Shima doing the logic and circuit design. Roger Swanson defined the new instructions for the 8085 while Peter Stoll and Andrew Volk performed the 8085 logic and circuit design. The 8086 architecture was defined by Stephen Morse and refined by Bruce Ravenel, with James McKevitt and John Bayliss responsible for the logic and circuit design. William Polhman managed both the 8085 and 8086 activities.

• 8087 (FPU) - John Palmer (Ravenel also involved, maybe led design?)
• 80186 - (Jim McKevitt?)
• 80286 - Bob Childs
• 80287 (FPU) -

• Intel IA32 - John Crawford and Patrick Gelsinger
• MMX extensions - Uri Weiser (chief), Alex Peleg (lead), Bob Dryer, Larry Mennemeier, David Bistry, and Millind Mittal
  • Uri Weiser, Trade-off Considerations and Performance of Intel's MMX Technology (Hot Chips 8 slides)
• MMX2 extensions -
• implementations
  • 80386 - John Crawford (chief), Jim Slager
  • 80387 (FPU) -
  • 80486, 1991 - John Crawford (chief)
  • Pentium (P5), 1993 - Don Alpert (chief), Jack Mills, Bob Dreyer, Ed Grochowski, and Uri Weiser
    • The initial superscalar definition and feasibility study for the Pentium was done by Uri Weiser, Yaakov Yaari, and David Perlmutter at Intel's Haifa Design Center in late 1988 / early 1989. Don Alpert and his team in Santa Clara started merging post-486 circuit designs into this superscalar framework in spring 1989.
    • John Crawford, Don Alpert, and Beatrice Fu, Pentium overview video, UVC, June 1993
    • Daniel Deleganes, Pentium 90/100 video (Hot Chips VI), UVC, August 1994
  • Pentium Pro (P6) - Bob Colwell (chief), Glenn Hinton (senior), Dave Papworth (senior), Michael Fetterman, and Andy Glew
    • IEEE Micro article
  • Pentium w/MMX (also includes PPro branch prediction), 1996
    • Michael Kagan, The P55C Microarchitecture: The First Implementation of MMX Technology (Hot Chips 8 slides)
  • Pentium II (Klamath) - same leaders as Pentium Pro
  • Willamette - Bob Colwell (chief), Glenn Hinton (lead), and Dave Papworth (senior)
• Merced (see independence arch. processor section)

NexGen

• Nx586 (F86), 1995 - Mack McFarland was the first architect, then Dave Stiles and Greg Favor worked on the design, and later Korbin Van Dyke oversaw the implementation
  • NexGen was a startup funded by Compaq, ASCII, and Kleiner Perkins (founder was Thampy Thomas); Nick Tredennick hired and managed the original engineering team; people who followed Nick included Atiq Raza and Dave Epstein (who led the chip into full production, 1990-1995)
  • the F86 was described at 1989 Compcon and later renamed Nx586, it required a FP coprocessor
  • NexGen was bought by AMD in 1995
• NexGen Nx686 (see AMD K6 above in this section)

Java processors

need intro...

Patriot Scientific Corp.

• PSC1000, 1997 -
  • 100 MHz, $10 in high volumes

Rockwell

• JEM1 - ? (Nick Mykris, mgr. of adv. uproc. section)
  • 50 MHz, 60 mW, based on AAMP rather than picoJava core

Sun JavaChips

• picoJava - Mike O'Connor, Marc Tremblay, Bill Joy
  • core design for use in other chips, treated as IP
  • IEEE Micro article
  • Marc Tremblay and Michael O'Connor, PicoJava: A hardware Implementation of the Java Virtual Machine (Hot Chips 8 slides)
    
• microJava 701, 1998 -
• ultraJava, ca. '98-99 - Marc Tremblay

Stack processors

The credit for collecting information in this section goes to Phil Koopman. He has found lots of designs but most with relatively low sales volume. Phil has a web page that points to current sales sources of stack processors.

Echelon

• Neuron, 1990 - Bruce Eisenhard
  • 8-bit, 3-way multithreaded communication microcontroller
  • sold as Motorola MC1431x0 and as Toshiba TMPN31x0

Harris

• RTX 2000 (based on Novix NC6000 design), 1987 - John Rible and Chris Malinowski
  • John Rible added on to the design of Novix NC4016 to create the NC6000 for Novix. Novix then licensed the design to Harris Semiconductor.
  • Chris Malinowski of Harris changed the NC6000 into a family of microcontrollers: RTX 2000, RTX 2001, RTX 2010.
  • Phil Koopman's description of the RTX 2000

Novix

• NC4016, 1985 - Chuck Moore (architect) with help from Bob Murphy and Greg Bailey
  • 16-bit, original "Forth Chip"
  • Implemented on a 4000-gate gate array
  • Phil Koopman's description of the NC4016
• NC6000, 1987 - John Rible (see Harris RTX 2000 above)

Embedded processors

more to do... (Phil Koopman describes this market in his 1996 ICCD paper.)

AMD (Advanced Micro Devices)

• 29000-derived (see workstation processor section)
  • 29030 - 2-bus, 8k icache, no dcache, interrupt controller, timer, jtag
  • 29035 - 2-bus, 4K icache, no dcache, interrupt controller, timer, jtag
  • 29040 - 2-bus, 8K icache, 4k dcache, interrupt controller, timer, jtag, hardware multiply
  • 29200 - 29000 core with parallel and serial ports, DMA, interrupt controller, DRAM, memory decode, and interface to laser printer engines
  • 29205 - slightly reduced function version of 29200
  • 29240 - like a 29200, with 4K icache, 2K dcache, hardware multiply, 16 entry MMU
  • 29245 - like a 29200, with 4K icache, 16 entry MMU
  • 29243 - like a 29240, 32 entry MMU, DRAM parity, no printer engine I/F
• x86-derived
  • Elan -

ARM (Advanced RISC Machines, Ltd.)

• ARM - Sophie Wilson (Also involved: Dave Jaggar wrote the ARMv4 Architecture book, David Seal oversaw the arithmetic, and Edward Nevill selected the Thumb opcodes after the basic idea was conceived by Dave Jaggar.)
  • ARM1 - Steve Furber (who now works at Manchester University on asynchronous ARMs called Amulet)
  • ARM2 - Steve Furber
  • ARM3 - Alasdair Thomas
  • [What happened to ARM4 and ARM5? That's when ARMltd was created from Acorn and Apple's Larry Tesler suggested a move to a consistent naming scheme - ARM6 for the core, ARM60 for a CPU chip (e.g. in the 3DO machine), ARM610 for an enhanced CPU with a cache (e.g. in the Newton or Acorn RiscPC). This scheme was later extended so that 4 digits is a deeply embedded processor with peripherals - most of these are based on ARM7 (ARM7500, ARM7500FE, ARM7110) with a couple of StrongARM1 based ones (SA1100, SA1500). Under this naming scheme, ARM1 would have been ARM10, ARM2 would have been ARM20, ARM3 would have been ARM200 (ARM2 plus cache) and ARM250 would have been ARM2500.]
  • ARM 6(10), 1993 - Alasdair Thomas
  • ARM 7(10), 1994 - Peter Harrod (?)
  • ARM 8(10), 1995 - Guy Larri, Neil Robinson
    • Guy Larri, ARM810: Dancing to the Beat of a Different Drum (Hot Chips 8 slides)
  • ARM9(10,40) - Ian Devereux, Guy Larri
  • ARMFPA11 - Peter Harrod, David Seal
  • ARM7500FE - Peter Harrod
  • see also Intel StrongARM in this section

Hitachi

• SuperH RISC -
  • SH-1/SH-2, 1993 -
  • SH-3, 1994 -
  • SH-4, 1997 -

Intel

• Intel 8051 - ? (8-bit?, check on this)
• Intel x86 derived
  • ...
• Intel i960 - Glen Myers
  • original implementation -
  • ...
  • i960 CA (superscalar), 1989 - Glenn Hinton and Frank Smith
  • i960 MM -
  • ...
  • SA,SB,KA,KB,JA,CF,HD,HT
  • R series has I2O
  • ...
  • i960 JX -
    • Richard Brunner, i960JX video (Hot Chips VI), UVC, August 1994
  • ...
  • i960 CA/MM/JX comparison
• StrongARM
  • DEC developed the StrongARM series of processors. As part of a lawsuit settlement between DEC and Intel, Intel acquired StrongARM.
  • Intel StrongArm page
  • StrongARM 110, 1996 - Rich Witek (lead), Greg Hoepnner, Ray Stephany, Jim Montanaro, +
    • Rich Witek and Kathy Snyder, DEC StrongArm video, UVC, Oct. 1996
    • Sribalan Santhanam, StrongArm 110: A 160MHz 32b 0.5W CMOS ARM Processor (Hot Chips 8 slides)
  • StrongARM 1100, 1997 - Rich Witek (lead)

MIPS

• MIPS-II-derived (32-bit, see workstation processor section)
• MIPS-16 (32-bit data/16-bit compressed instructions), 1996 - Earl Killian and Hartvig Ekner

Motorola

• 68000-derived
  • 68060 (see workstation processor section)
  • 68300 (??)
• M-CORE -
• Coldfire - Joe Circello
  • Motorola Unfolds ColdFire Roadmap, Microprocessor Report, September 16, 1996 [check if on-line]
  • ColdFire: A Hot Architecture, Byte, May 1995 [get link to on-line copy]
  • 5102, 1995 -
  • 520x? -
• PowerPC-derived
  • 400 series ...
  • 500 series ...
  • 602?
  • 800 series ...

National Semiconductor

• Embedded versions of National Semiconductor 32K
  • NS32CG16 (Guppy) - based on the original 32016 without MMU support but with added software and hardware bitblt support, used in the Canon LBP printer
  • NS32CG160 (Shark) - uses same core as Guppy (CG) and adds timers, DMAC, and ICU; designed for LBP
  • NS32FX16 (Goldfish, a.k.a. Wanda) - used the CG core and added a DSP accelerator designed specifically for fax applications where the integer machine will do the printing and the DSP part will do a soft modem
  • NS32FX164/161 and 32FV16 (with various on-chip RAM and Sigma-Delta codec configurations, Goldfish-II) - used the same core as Goldfish but with a more aggressive DSP accelerator, biggest success was as the sole processing unit within the HP OfficeJet (responsible for everything starting with the modem and ending with rendering and printing)
  • NS32AM160/161/162/163 - all with the same processing units as the Goldfish-II and added circuitry required to implement a Digital Answering Machine, first or one of the first full system-on-a-chip solutions, with biggest success being the whole family of AT&T digital answering machines
  • NS32GX320 (Barracuda) - used the 32532 core minus the on-chip MMU, used in multifunction peripherals
• CompactRISC - CR16A and CR32A done by Gideon Intrater, and CR16B done by Alon Naveh
  • CompactRISC is a load/store architecture with a fixed-length instruction format that implements a very small subset of the original NS32K instruction set. Traps are treated similarly; but the register file is significantly larger. Additionally, there are some new DSP instructions and a new calling convention.
  • See also D. Alpert, A. Averbuch, and O. Danieli, "Performance comparison of load/store and symmetric instruction set architectures," ISCA-17, Seattle, 1990, pp. 172-181.
  • Implementations
    • NS32SF641 - essentially the Swordfish design changed to implement the CompactRISC inst. set - Gideon Intrater took over responsibility for the design after Don Alpert left for Intel
    • Piranha, 1995 - Gideon Intrater
    • HPC (embedded 16-bit) - Ralph Haines
• Intel x86 derived
  • NS486 embedded controller - Mario Nemirovsky & others

Rockwell

• AAMP -
• JEM1 (see Java processor section)

Transputer

• Transputer - Iann Barron (main), David May, Roger Shepherd, and Peter Thompson
  • Iann Barron was the main architect and was responsible for putting the team together and providing the concepts.
  • David May provided the principal details of the transputer instruction set, its communications, and the occam language.
  • Roger Shepherd, under David May's guidance, provided the details of the timer.
  • Peter Thompson developed the communications architecture of IEEE 1355, with its simple but flexible virtual channels and hardware routing technology.
  • "All the ideas were bounced off other people, many of whom contributed by asking awkward questions, finding holes in what was proposed, simply writing down what was proposed, trying to implement it and finding awkwardnesses that needed to be cleaned up, and even asking customers what they wanted. But none of these people would have come together without Iann Barron."
• implementations
  • various test chips
  • T4 - Guy Harriman
  • T8 - Mark Homewood
  • T9 - Brian Parsons
  • ST20 embedded processor - Bob Krysiak

  • Transputer archive
  • T9000 paper

DSP processors

to be done

Texas Instruments

• TMS320 series
  • The speech synthesis chip developed by George L. Brantingham and Richard H. Wiggins in 1978 (U.S. Patent No. 4,209,844 granted in 1980) was the beginning of TI's DSP efforts. It used an on-chip 8-bit digital-to-analog converter to transform digital information processed through the filter into synthetic speech. It used a multistage multiplier and accumulator architecture.
  • TMS320C3x - first 32-bit single-chip floating-point DSP
  • TMS320C4x - first multiprocessing DSP easily interconnectable in various configurations of meshes, grids, rings, etc.
  • TMS320C6x - first single-chip 8-wide-VLIW DSP (see VLIW processor section)

Selected game processors

... more to do

Nintendo 64

• main processor is a MIPS R4300 (slightly modified)
• Reality Co Processor (RCP) - team effort
  • Mary Jo Doherty was the lead designer for the (RSP) signal processor portion of the chip
  • Phil Gossett was the lead designer for the (RDP) graphics portion of the chip
  • Tim van Hook brought many ideas to the RCP from his earlier work with the "MIPS Multi Media Engine"

Sony Playstation 2

• Masaaki Oka and Masakazu Suzuoki, "Programming the Emotion Engine," IEEE Micro, Vol.19, No. 6, November/December 1999

Acknowledgements

My thanks to the following for their help in identifying some of the folks listed above and telling me about the projects in which they were involved: Don Alpert, Mitch Alsup, Steve Anderson, Pete Bannon, Allen Baum, Rich Belgard, Dave Bernstein, Mark Bluhm, Joel Boney, David Boreham, David Boundy, Henry Burkhardt III , Bob Colwell, Charlie Crabb, Jim Dehnert, Marvin Denman, Keith Diefendorff, John Edmondson, Dave Epstein, Alan Folmsbee, Philip Freidin, Robert Garner, Greg Grohoski, Mike Haertel, Andrew Haley, Jan Hoogerbrugge, Marty Hopkins, Gideon Intrater, Earl Killian, Phil Koopman, Ashok Kumar, Steven Kunkel, Dan Lau, Guy Lemieux, Richard Lethin, John Mashey, Shawn McLean, Avraham Menachem, Steve Morse, Steve Muchnick, Harm Munk, Michael O'Connor, Tim Olson, Howard Owens, Yale Patt, Dave Patterson, John Ruttenberg, Ulf Samuelsson, Ray Simar, Peter Song, Zalman Stern, H.W. Stockman, Bob Supnik, Ran Talmudi, Ross Towle, Nick Tredennick, Marc Tremblay, Stuart Tucker, Paul Walker, Uri Weiser, Turner Whitted, Sophie Wilson, Steve Wilson, Bill Worley, Mike Ziegler. (My apologies to these individuals for any misunderstandings on my part about the information they have graciously shared with me; the errors in the architects list above remain mine.)

Revision history

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