DA53	TXA         ;A=0
DA54	LDX #&E2    ;X=&E2
DA56	STA &00,X   ;zero zeropage &E2 to &FF
DA58	INX         ;
DA59	BNE &DA56   ;X=0

DA5B	LDA &D93F,Y ;copy data from &D93F+Y
DA5E	STA &01FF,Y ;to &1FF+Y
DA61	DEY         ;until
DA62	BNE &DA5B   ;1FF+Y=&200

DA64	LDA #&62    ;A=&62
DA66	STA &ED     ;store in &ED
DA68	JSR &FB0A   ;set up ACIA
   		    ;X=0
************** clear interrupt and enable registers of Both VIAs ********

DA6B	LDA #&7F    ;
DA6D	INX         ;
DA6E	STA &FE4D,X ;
DA71	STA &FE6D,X ;
DA74	DEX         ;
DA75	BPL &DA6E   ;

DA77	CLI         ;briefly allow interrupts to clear anything pending
DA78	SEI         ;disallow again N.B. All VIA IRQs are disabled
DA79	BIT &FC     ;if bit 6=1 then JSR &F055 (normally 0)
DA7B	BVC &DA80   ;else DA80
DA7D	JSR &F055   ;F055 JMP (&FDFE) probably causes a BRK unless
   		    ;hardware there redirects it.
   		    ;
DA80	LDX #&F2    ;enable interrupts 1,4,5,6 of system VIA
DA82	STX &FE4E   ;
   		    ;0      Keyboard enabled as needed
   		    ;1      Frame sync pulse
   		    ;4      End of A/D conversion
   		    ;5      T2 counter (for speech)
   		    ;6      T1 counter (10 mSec intervals)
   		    ;
DA85	LDX #&04    ;set system VIA PCR
DA87	STX &FE4C   ;
   		    ;CA1 to interrupt on negative edge (Frame sync)
   		    ;CA2 Handshake output for Keyboard
   		    ;CB1 interrupt on negative edge (end of conversion)
   		    ;CB2 Negative edge (Light pen strobe)
   		    ;
DA8A	LDA #&60    ;set system VIA ACR
DA8C	STA &FE4B   ;
   		    ;disable latching
   		    ;disable shift register
   		    ;T1 counter continuous interrupts
   		    ;T2 counter timed interrupt

DA8F	LDA #&0E    ;set system VIA T1 counter (Low)
DA91	STA &FE46   ;
   		    ;this becomes effective when T1 hi set

DA94	STA &FE6C   ;set user VIA PCR
   		    ;CA1 interrupt on -ve edge (Printer Acknowledge)
   		    ;CA2 High output (printer strobe)
   		    ;CB1 Interrupt on -ve edge (user port)
   		    ;CB2 Negative edge (user port)

DA97	STA &FEC0   ;set up A/D converter
   		    ;Bits 0 & 1 determine channel selected
   		    ;Bit 3=0 8 bit conversion bit 3=1 12 bit

DA9A	CMP &FE6C   ;read user VIA IER if = &0E then DAA2 chip present
DA9D	BEQ &DAA2   ;so goto DAA2
DA9F	INC &0277   ;else increment user VIA mask to 0 to bar all
   		    ;user VIA interrupts

DAA2	LDA #&27    ;set T1 (hi) to &27 this sets T1 to &270E (9998 uS)
DAA4	STA &FE47   ;or 10msec, interrupts occur every 10msec therefore
DAA7	STA &FE45   ;

DAAA	JSR &EC60   ;clear the sound channels

DAAD	LDA &0282   ;read serial ULA control register
DAB0	AND #&7F    ;zero bit 7
DAB2	JSR &E6A7   ;and set up serial ULA

DAB5	LDX &0284   ;get soft key status flag
DAB8	BEQ &DABD   ;if 0 (keys OK) then DABD
DABA	JSR &E9C8   ;else reset function keys



*************************************************************************
*                                                                       *
*       Check sideways ROMS and make rom list                           *
*                                                                       *
*************************************************************************
   	
   		    ;X=0
DABD	JSR &DC16   ;set up ROM latch and RAM copy to X
DAC0	LDX #&03    ;set X to point to offset in table
DAC2	LDY &8007   ;get copyright offset from ROM

   		    ; DF0C = ")C(",0
DAC5	LDA &8000,Y ;get first byte
DAC8	CMP &DF0C,X ;compare it with table byte
DACB	BNE &DAFB   ;if not the same then goto DAFB
DACD	INY         ;point to next byte
DACE	DEX         ;(s)
DACF	BPL &DAC5   ;and if still +ve go back to check next byte

   		    ;this point is reached if 5 bytes indicate valid
   		    ;ROM (offset +4 in (C) string)


*************************************************************************
* Check first 1k of each ROM against higher priority Roms to ensure that*
* there are no matches, if a match found ignore lower priority ROM      *
*************************************************************************

DAD1	LDX &F4     ;get RAM copy of ROM No. in X
DAD3	LDY &F4     ;and Y

DAD5	INY         ;increment Y to check
DAD6	CPY #&10    ;if ROM 15 is current ROM
DAD8	BCS &DAFF   ;if equal or more than 16 goto &DAFF
   		    ;to store catalogue byte
DADA	TYA         ;else put Y in A
DADB	EOR #&FF    ;invert it
DADD	STA &FA     ;and store at &FA
DADF	LDA #&7F    ;store &7F at
DAE1	STA &FB     ;&FB to get address &7FFF-Y

DAE3	STY &FE30   ;set new ROM
DAE6	LDA (&FA),Y ;Get byte
DAE8	STX &FE30   ;switch back to previous ROM
DAEB	CMP (&FA),Y ;and compare with previous byte called
DAED	BNE &DAD5   ;if not the same then go back and do it again
   		    ;with next rom up
DAEF	INC &FA     ;else increment &FA to point to new location
DAF1	BNE &DAE3   ;if &FA<>0 then check next byte
DAF3	INC &FB     ;else inc &FB
DAF5	LDA &FB     ;and check that it doesn't exceed
DAF7	CMP #&84    ;&84 (1k checked)
DAF9	BCC &DAE3   ;then check next byte(s)

DAFB	LDX &F4     ;X=(&F4)
DAFD	BPL &DB0C   ;if +ve then &DB0C

DAFF	LDA &8006   ;get rom type
DB02	STA &02A1,X ;store it in catalogue
DB05	AND #&8F    ;check for BASIC (bit 7 not set)
DB07	BNE &DB0C   ;if not BASIC the DB0C
DB09	STX &024B   ;else store X at BASIC pointer


DB0C	INX         ;increment X to point to next ROM
DB0D	CPX #&10    ;is it 15 or less
DB0F	BCC &DABD   ;if so goto &DABD for next ROM