An interface has been added to allow 6502 paged ROM images to be developed
which make access to RISC OS SWIs. The SWI is called by executing a
previously undefined 6502 opcode.

NB This will not work in the main memory, only in a paged ROM

NB2 This is the same protocol that !65Host uses to issue SWIs

6502 Opcode &07 - Issue SWI call

in:     XY (X lo-byte, Y hi-byte) points to control block (cb)

cb?0..2 = SWI number (lo..hi) (bit 17 set => return errors with V set)

cb?3    = number of registers to put back into block on exit, starting at
	   R0

cb?4    = bit set of registers to relocate on entry to SWI
          (bit n set => relocate Rn from 6502 to ARM address space)

cb?5    = bit set of registers to unrelocate on exit from SWI
          (bit n set => unrelocate Rn from ARM to 6502 address space)

cb?6,7  = address (lo,hi) of error buffer (in 6502 space)
          only relevant if bit 17 of SWI number set

cb?8    = length of error buffer (can be zero)

cb!9    = register R0

cb!13   = register R1

..

cb!37   = register R7

out:    A,X,Y preserved
        N,Z,C,V as returned by the ARM on exit from the SWI
        Some or all of the register block is updated with the
        values on exit (possibly relocated), as controlled by cb?3,4,5

        If bit 17 of the SWI number was clear, and an error occurs, then
        control will not returned to the 6502 code - instead the error
        block is copied to &100 in 6502 format (ie zero byte, 1 byte error
        number, followed by zero terminated error string) and then it jumps
        to &100, which causes a BRK. If no error occurred, control will be
        returned and V will be clear.

        If bit 17 of the SWI number was set, then the X form of the SWI
        is issued; if this returns with V set, then the error block is
        copied into the specified error buffer in 6502 format, truncated
        to the length of the error buffer (if truncated the terminating
        zero will be in the last byte of the error buffer).