Full 6809/6809e/6309 Opcode List Including Undocumented Opcodes =============================================================== File: DOCS.Comp.6809.OpList - Update: 0.10 Author: J.G.Harston - Date: 08-08-2001 This attempts to be a full list of all the opcodes on the 6809/6809e and 6309. Opcodes marked with a * are only available on the 6309. nn nn 10 nn 11 nn ------------------------------------------------------------------------ 00 NEG ext - - 71 *OIM >ext - - 72 *AIM >ext - - 73 COM >ext - - 74 LSR >ext - - 75 *EIM >ext - - 76 ROR >ext - - 75 EIM >ext - - 77 ASR >ext - - 78 ASL >ext - - 79 ROL >ext - - 7A DEC >ext - - 7B *TIM >ext - - 7C INC >ext - - 7D TST >ext - - 7E JMP >ext - - 7F CLR >ext - - 80 SUBA #n *SUBW #n16 *SUBE #n 81 CMPA #n *CMPW #n16 *CMPE #n 82 SBCA #n *SBCD #n16 - 83 SUBD #n16 CMPD #n16 CMPU #n16 84 ANDA #n *ANDD #n16 - 85 BITA #n *BITD #n16 - 86 LDA #n *LDW #n16 *LDE #n 87 - - - 88 EORA #n *EORD #n16 - 89 ADCA #n *ADCD #n16 - 8A ORA #n *ORD #n16 - 8B ADCA #n *ADDW #n16 *ADDE #n 8C CPX #n16 CMPY #n16 CMPS #n16 8D BSR rel - *DIVD #n16 8E LDX #n16 LDY #n16 *DIVQ #n16 8F - - *MULD #n16 90 SUBA ext *SUBW >ext *SUBE >ext B1 CMPA >ext *CMPW >ext *CMPE >ext B2 SBCA >ext *SBCD >ext - B3 SUBD >ext CMPD >ext CMPU >ext B4 ANDA >ext *ANDD >ext - B5 BITA >ext *BITD >ext - B6 LDA >ext *LDW >ext *LDE >ext B7 STA >ext *STW >ext *STE >ext B8 EORA >ext *EORD >ext - B9 ADCA >ext *ADCD >ext - BA ORA >ext *ORD >ext - BB ADDA >ext *ADDW >ext *ADDE >ext BC CMPX >ext CMPY >ext CMPS >ext BD JSR >ext - *DIVD >ext BE LDX >ext LDY >ext *DIVQ >ext BF STX >ext LDS >ext *MULD >ext C0 SUBB #n - *SUBF #n C1 CMPB #n - *CMPF #n C2 SBCB #n - - C3 ADDD #n16 - - C4 ANDB #n - - C5 BITB #n - - C6 LDB #n - *LDF #n C7 - - - C8 EORB #n - - C9 ADCB #n - - CA ORB #n - - CB ADDB #n - *ADDF #n CC LDD #n16 - - CD *LDQ #n32 - - CE LDU #n16 LDS #n16 - CF - - - D0 SUBB ext - *SUBF >ext F1 CMPB >ext - *CMPF >ext F2 SBCB >ext - - F3 ADDD >ext - - F4 ANDB >ext - - F5 BITB >ext - - F6 LDB >ext - *LDF >ext F7 STB >ext - *STF >ext F8 EORB >ext - - F9 ADCB >ext - - FA ORB >ext - - FB ADDB >ext - *ADDF >ext FC LDD >ext *LDQ >ext - FD STD >ext *STQ >ext - FE LDU >ext LDS >ext - FF STU >ext STS >ext - Operands -------- n - 8bit number n16 - 16bit number n32 - 32bit number extend - 16bit absolute address rel - 8bit relative offset rel16 - 16bit relative offset regs - register map idx - indexed addressing mode, see n>ext table Indexed Addressing Mode ----------------------- In indexed addressing mode the referenced data is specified by a post-byte Idx addressing mode: Specified by a post-byte, after the opcode and before any additional data. 0rrnnnnn n,R 1rr00000 ,R+ 1rr00001 ,R++ 1rr00010 ,-R 1rr00011 ,--R 1rr00100 ,R 1rr00101 B,R 1rr00110 A,R 1??00111 1rr01000 nnnnnnnn n,R 1rr01001 nnnnnnnn nnnnnnnn nn,R 1??01010 1rr01011 D,R 1xx01100 nnnnnnnn n,PCR 1xx01101 nnnnnnnn nnnnnnnn nn,PCR 1??01110 1??01111 1??10000 1rr10001 [,R++] 1??10010 1rr10011 [,--R] 1rr10100 [,R] 1rr10101 [B,R] 1rr10110 [A,R] 1??10111 1rr11000 nnnnnnnn [n,R] 1rr11001 nnnnnnnn nnnnnnnn [nn,R] 1??11010 1rr11011 [D,R] 1xx11100 nnnnnnnn [n,PCR] 1xx11101 nnnnnnnn nnnnnnnn [n,PCR] 1??11110 10011111 nnnnnnnn nnnnnnnn [nn] 10111111 11011111 11111111 rr=X,Y,U,S 5-bit positive offset from X in 6800 code translates to the same 5-bit offset from X in 6809. LDAA 1,X in 6800: 86 01 LDA 1,X in 6809: 86 0rr00001 where rr=0 gives: 86 01 It seems to be incredibly difficult to track down information on the inctruction set for the 6809 and similar CPUs. Even when information is found it is really fiddly to understand. The only difference between the 6809 and the 6809e is the pinouts. The instruction set is the same. The 6309 is a further develpment by Hitatchi with more instructions and registers. The 6800 series are bigendian, that is, multibyte values are stored in memory with the most significant byte first. Idx mode on the 6800 adds an offset to the 16bit X register to form the address in memory of the data. Idx mode on the 6809/6309 is complicated. A byte follows the opcode bytes(s) which indicates which register is idxed from and how that idxing register is combined with the supplied offset. It's quite fiddly and annoyingly difficult to track down accurate and clear information. LDA idx E6 nn ">Extended": specifies memory address, data is contents of memory location. Other CPUs call this "absolute". "Direct": specifies an 8-bit address in zero page, later CPUs in "Direct page". 6502 calls this Zero Page addressing "Idxed": specifies 8-bit offset from value of X register. r0,r1 - n>ext byte contains [The 6809 series of CPUs appears to have a really fiddly instruction set to work out the opcodes for. It also seems to be very difficult to actually track down the required information to put together a document such as this.] HORRIBLE HORRIBLE HORRIBEL! it(s getting easier, but God!, it's difficult tracking down info! The only difference I can find between the 6809 and the 6809e is the pinouts: 6809: Halt, XTAL, >EXTAL, Reset, MRDY, Q, E, DMA/BREQ 6809e: Halt, TSC, LIC, Reset, AVMA, Q, E, Busy Also, many instructions take a "post-byte" that specifies the source and destination of the operation, effectively creating almost a 16-bit opcode space. Instructions seem to be the "wrong" way around. For example, to add a constant to a register is ADCA