Date : Tue, 22 Sep 1998 12:43:16 +-200
From : Carlo Concari <conca@...>
Subject: R: 65C02 vs. 65C12 and Acorn ROMS
Yes! Now there's an ISP in my telephone area, so now I have Internet access
at home!!! Well, yes, ok, I know, noone cares...
Stuart William McConnachie wrote:
>The only big difference I'm aware of is that the 65C02 has four
>instructions that are not implemented on the 65C12: BBR, BBS, RMB, SMB.
Could you tell me what their op-codes are and what they do!
RMB ans SMB stand for (Re)Set Memory Bit. They set or reset a bit in zero
page. They take up 2 bytes and 5 ticks. Naturally, the operand is the address
in page 0. For each instruction there are 8 opcodes, one for bit position.
RMB are opcodes 07 to 77; the most significant nibble refers to the bit
position,
while the LSD is always 7. SMB takes up opcodes 87 to F7.
So, if you type RMB4 &72 the assembler will translate it into 47 72 and the
instruction will put 0 in bit 4 of address &72.
BBR and BBS are more complicated in that they take two operands; the first
one is an address in zero page, while the latter is a relative offset (just
like the
ones in Branch istructions). BBR# and BBS# branch if the #'th bit of the zero
page operand is respectively 0 or 1. Unfortunately I dont't know the asm syntax
nor do I know where the jump offset is calculated from (i.e. I don't know if an
offset of &00 would jump to the next istruction or to the middle of the current
one or anywhere else). The opcodes for these two instructions end in F; BBR
takes up opcodes 0F - 7F, while BBS takes 8F - FF. Each takes up 3 bytes
and 5 clock cycles.
Weel, this is all I know about them. Hope that's enough :-)
>The 65C12 treats these four instructions as NOPs.
As it does all other illegal op-codes.
Yes.
Just a little curious. I could measure them myself, but if you've
already done the work it would be useful to see. Cheers.
Do you also know the cycle counts for the legal instructions. I belive
these are different than for the original 6502. BTW is that correctly
called a 6502A, and if so why have I never heard of a 6502B (Or is that
a stupid question?)
Well, I think the 6502A is an improvement (don't know in which ways) of the
original 6502. Don't know anything about the 6502B though.
At the end of my message you can find the correct timings for the 65C12
instructions.
Sorry for the excessive length of this message, but this list is here for us
emulator writers to share our knowledge, isn't it? >:->
65c12 Opcode table
LSD 0 1 2 3 4 5 6 7
MSD BRK ORA NOP NOP *TSB ORA ASL NOP
0 implied (ind,x) zp zp zp
1 7 2 6 2 2 1 1 2 5 2 3 2 5 1 1
BPL ORA *ORA NOP TRB ORA ASL NOP
1 Rel (ind),y (ind) zp zp,x zp,x
2 2** 2 5* 2 5 1 1 2 5 2 4 2 6 1 1
JSR AND NOP NOP BIT AND ROL NOP
2 ABS (ind,x) zp zp zp
3 6 2 6 2 2 1 1 2 3 2 3 2 5 1 1
BMI AND *AND NOP *BIT AND ROL NOP
3 rel (ind),y (ind) zp,x zp,x zp,x
2 2** 2 5* 2 5 1 1 2 4 2 4 2 6 1 1
RTI EOR NOP NOP NOP EOR LSR NOP
4 implied (ind,x) zp zp
1 6 2 6 2 2 1 1 2 3 2 3 2 5 1 1
BVC EOR *EOR NOP NOP EOR LSR NOP
5 rel (ind),y (ind) zp,x zp,x 1 1
2 2** 2 5* 2 5 1 1 2 4 2 4 2 6 2 5
RTS ADC NOP NOP *STZ ADC ROR NOP
6 implied (ind,x) zp zp zp
1 6 2 6+ 2 2 1 1 2 3 2 3+ 2 5 1 1
BVS ADC *ADC NOP *STZ ADC ROR NOP
7 rel (ind),y (ind) zp,x zp,x zp,x
2 2** 2 5*+ 2 5+ 1 1 2 4 2 4+ 2 6 1 1
*BRA STA NOP NOP STY STA STX NOP
8 rel (ind,x) zp zp zp
2 3* 2 6 2 2 1 1 2 3 2 3 2 3 1 1
BCC STA *STA NOP STY STA STX NOP
9 rel (ind),y (ind) zp,x zp,x zp,x
2 2** 2 6 2 5 1 1 2 4 2 4 2 4 1 1
LDY LDA LDX NOP LDY LDA LDX NOP
A imm (ind,x) imm zp zp zp
2 2 2 6 2 2 1 1 2 3 2 3 2 3 1 1
BCS LDA *LDA NOP LDY LDA LDX NOP
B rel (ind),y (ind) zp,x zp,x zp,x
2 2** 2 5* 2 5 1 1 2 4 2 4 2 4 1 1
CPY CMP NOP NOP CPY CMP DEC NOP
C imm (ind,x) zp zp zp
2 2 2 6 2 2 1 1 2 3 2 3 2 5 1 1
BNE CMP *CMP NOP NOP CMP DEC NOP
D rel (ind),y (ind) zp,x zp,x
2 2** 2 5* 2 5 1 1 2 4 2 4 2 6 1 1
CPX SBC NOP NOP CPX SBC INC NOP
E imm (ind,x) zp zp zp
2 2 2 6+ 2 2 1 1 2 3 2 3+ 2 5 1 1
BEQ SBC *SBC NOP NOP SBC INC NOP
F rel (ind),y (ind) zp,x zp,x
2 2** 2 5*+ 2 5+ 1 1 2 4 2 4+ 2 6 1 1
LSD 8 9 A B C D E F
MSD PHP ORA ASL NOP *TSB ORA ASL NOP
0 implied imm acc abs abs abs
1 3 2 2 1 2 1 1 3 6 3 4 3 6 1 1
CLC ORA *INC NOP *TRB ORA ASL NOP
1 impied abs,y acc abs abs,x abs,x
1 2 3 4* 1 2 1 1 3 6 3 4* 3 6 1 1
PLP AND ROL NOP BIT AND ROL NOP
2 implied imm acc abs abs abs
1 4 2 2 1 2 1 1 3 4 3 4 3 6 1 1
SEC AND *DEC NOP *BIT AND ROL NOP
3 impied abs,y acc abs,x abs,x abs,x
1 2 3 4* 1 2 1 1 3 4* 3 4* 3 6 1 1
PHA EOR LSR NOP JMP EOR LSR NOP
4 implied imm acc abs abs abs
1 3 2 2 1 2 1 1 3 3 3 4 3 6 1 1
CLI EOR *PHY NOP NOP EOR LSR NOP
5 impied abs,y acc abs,x abs,x
1 2 3 4* 1 3 1 1 3 8 3 4* 3 6 1 1
PLA ADC ROR NOP JMP ADC ROR NOP
6 implied imm acc (abs) abs abs
1 4 2 2+ 1 2 1 1 3 6 3 4+ 3 6 1 1
SEI ADC *PLY NOP *JMP ADC ROR NOP
7 impied abs,y implied (abs,x) abs,x abs,x
1 2 3 4*+ 1 4 1 1 3 6 3 4*+ 3 6 1 1
DEY *BIT TXA NOP STY STA STX NOP
8 implied imm implied abs abs abs
1 2 2 2 1 2 1 1 3 4 3 4 3 4 1 1
TYA STA TXS NOP *STZ STA *STZ NOP
9 impied abs,y implied abs abs,x abs,x
1 2 3 5 1 2 1 1 3 4 3 5 3 5 1 1
TAY LDA TAX NOP LDY LDA LDX NOP
A implied imm implied abs abs abs
1 2 2 2 1 2 1 1 3 4 3 4 3 4 1 1
CLV LDA TSX NOP LDY LDA LDX NOP
B impied abs,y implied abs,x abs,x abs,y
1 2 3 4* 1 2 1 1 3 4* 3 4* 3 4* 1 1
INY CMP DEC NOP CPY CMP DEC NOP
C implied imm implied abs abs abs
1 2 2 2 1 2 1 1 3 4 3 4 3 6 1 1
CLD CMP *PHX NOP NOP CMP DEC NOP
D impied abs,y implied abs,x abs,x
1 2 3 4* 1 3 1 1 3 4 3 4* 3 6 1 1
INX SBC NOP NOP CPX SBC INC NOP
E implied imm implied abs abs abs
1 2 2 2+ 1 2 1 1 3 4 3 4+ 3 6 1 1
SED SBC *PLX NOP NOP SBC INC NOP
F impied abs,y implied abs,x abs,x
1 2 3 4*+ 1 4 1 1 3 4 3 4*+ 3 6 1 1
2 5 Instruction Bytes, Machine Cycles
For "Machine Cycles":
+ Add 1 in decimal mode
* Add 1 if page boundary is crossed
** Add 1 if branch occurs, 2 is branch occurs to different page
Ciao to all,
Carlo.